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d59271c7b7
Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1525713 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*
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* GP10B GPU GR
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*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _NVGPU_GR_GP10B_H_
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#define _NVGPU_GR_GP10B_H_
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#include <linux/version.h>
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#include "gk20a/mm_gk20a.h"
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struct gk20a;
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struct gr_gk20a_isr_data;
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enum {
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PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
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PASCAL_A = 0xC097,
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PASCAL_COMPUTE_A = 0xC0C0,
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PASCAL_DMA_COPY_A = 0xC0B5,
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PASCAL_DMA_COPY_B = 0xC1B5,
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};
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#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c
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#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc
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#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028
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#define NVC097_SET_RD_COALESCE 0x102c
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#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280
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#define NVC097_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC097_SET_BES_CROP_DEBUG3 0x10c4
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#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528
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#define NVC0C0_SET_RD_COALESCE 0x0228
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void gp10b_init_gr(struct gk20a *g);
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int gr_gp10b_init_fs_state(struct gk20a *g);
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int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
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struct nvgpu_mem *mem);
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void gr_gp10b_create_sysfs(struct device *dev);
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int gr_gp10b_handle_fecs_error(struct gk20a *g,
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struct channel_gk20a *__ch,
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struct gr_gk20a_isr_data *isr_data);
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int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
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struct channel_gk20a *fault_ch);
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struct gr_t18x {
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struct {
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u32 preempt_image_size;
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0)
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u32 force_preemption_gfxp;
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u32 force_preemption_cilp;
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u32 dump_ctxsw_stats_on_channel_close;
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#else
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bool force_preemption_gfxp;
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bool force_preemption_cilp;
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bool dump_ctxsw_stats_on_channel_close;
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#endif
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struct dentry *debugfs_force_preemption_cilp;
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struct dentry *debugfs_force_preemption_gfxp;
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struct dentry *debugfs_dump_ctxsw_stats;
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} ctx_vars;
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u32 fecs_feature_override_ecc_val;
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int cilp_preempt_pending_chid;
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};
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struct gr_ctx_desc_t18x {
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struct nvgpu_mem preempt_ctxsw_buffer;
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struct nvgpu_mem spill_ctxsw_buffer;
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struct nvgpu_mem betacb_ctxsw_buffer;
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struct nvgpu_mem pagepool_ctxsw_buffer;
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u32 ctx_id;
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bool ctx_id_valid;
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bool cilp_preempt_pending;
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};
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#endif
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