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6c3c360462
IRQs can get triggered during nvgpu power-on due to MMU fault, invalid PRIV ring or bus access etc. Handlers for those IRQs can't access the full state related to the IRQ unless nvgpu is fully powered on. In order to let the IRQ handlers know about the nvgpu power-on state gk20a.power_on_state variable has to be protected through spinlock to avoid the deadlock due to usage of earlier power_lock mutex. Further the IRQs need to be disabled on local CPU while updating the power state variable hence use spin_lock_irqsave and spin_unlock_- irqrestore APIs for protecting the access. JIRA NVGPU-1592 Change-Id: If5d1b5e2617ad90a68faa56ff47f62bb3f0b232b Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2203860 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
86 lines
2.6 KiB
C
86 lines
2.6 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifdef CONFIG_NVGPU_TRACE
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#include <trace/events/gk20a.h>
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#endif
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#include <nvgpu/mm.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/hw/gk20a/hw_flush_gk20a.h>
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#include "flush_gk20a.h"
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#ifdef CONFIG_NVGPU_COMPRESSION
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void gk20a_mm_cbc_clean(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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u32 data;
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struct nvgpu_timeout timeout;
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u32 retries = 200;
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nvgpu_log_fn(g, " ");
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gk20a_busy_noresume(g);
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if (nvgpu_is_powered_off(g)) {
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goto hw_was_off;
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}
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if (g->ops.mm.get_flush_retries != NULL) {
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retries = g->ops.mm.get_flush_retries(g, NVGPU_FLUSH_CBC_CLEAN);
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}
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nvgpu_assert(nvgpu_timeout_init(g, &timeout, retries,
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NVGPU_TIMER_RETRY_TIMER) == 0);
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nvgpu_mutex_acquire(&mm->l2_op_lock);
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/* Flush all dirty lines from the CBC to L2 */
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nvgpu_writel(g, flush_l2_clean_comptags_r(),
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flush_l2_clean_comptags_pending_busy_f());
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do {
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data = nvgpu_readl(g, flush_l2_clean_comptags_r());
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if (flush_l2_clean_comptags_outstanding_v(data) ==
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flush_l2_clean_comptags_outstanding_true_v() ||
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flush_l2_clean_comptags_pending_v(data) ==
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flush_l2_clean_comptags_pending_busy_v()) {
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nvgpu_log_info(g, "l2_clean_comptags 0x%x", data);
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nvgpu_udelay(5);
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} else {
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break;
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}
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} while (nvgpu_timeout_expired_msg(&timeout,
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"l2_clean_comptags too many retries") == 0);
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nvgpu_mutex_release(&mm->l2_op_lock);
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hw_was_off:
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gk20a_idle_nosuspend(g);
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}
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#endif
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