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80adcd99e8
Fixes issues related to MISRA 10.6 in hal ltc driver. JIRA NVGPU-3422 Change-Id: Ic2ebd879d35619a92d7354490cff605ea22c43b0 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2119972 GVS: Gerrit_Virtual_Submit Reviewed-by: Philip Elcan <pelcan@nvidia.com> Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
61 lines
2.1 KiB
C
61 lines
2.1 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/types.h>
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#include <nvgpu/ltc.h>
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#include <nvgpu/comptags.h>
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#include <nvgpu/io.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/gk20a.h>
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#include <trace/events/gk20a.h>
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#include "ltc_tu104.h"
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#include "ltc_gv11b.h"
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#include <nvgpu/hw/tu104/hw_ltc_tu104.h>
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void ltc_tu104_init_fs_state(struct gk20a *g)
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{
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u32 reg;
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u32 line_size = 512U;
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gv11b_ltc_init_fs_state(g);
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reg = nvgpu_readl(g, ltc_ltcs_ltss_cbc_param2_r());
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g->ltc->slices_per_ltc =
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ltc_ltcs_ltss_cbc_param2_slices_per_ltc_v(reg);
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g->ltc->cacheline_size =
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line_size << ltc_ltcs_ltss_cbc_param2_cache_line_size_v(reg);
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/* disable PLC compression */
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reg = nvgpu_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r());
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reg = set_field(reg,
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ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_m(),
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ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_plc_disabled_f());
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reg = set_field(reg,
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ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_m(),
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ltc_ltcs_ltss_tstg_set_mgmt_1_plc_recompress_rmw_disabled_f());
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nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r(), reg);
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}
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