mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
c270bb73ae
Renamed the following HALs - syncpt.alloc_syncpt_buf -> syncpt.alloc_buf - syncpt.free_syncpt_buf -> syncpt.free_buf - syncpt.add_syncpt_wait_cmd -> syncpt.add_wait_cmd - syncpt.get_syncpt_wait_cmd_size -> syncpt.get_wait_cmd_size - syncpt.get_syncpt_incr_per_release -> syncpt.get_incr_per_release - syncpt.add_syncpt_incr_cmd -> syncpt.add_incr_cmd - syncpt.get_syncpt_incr_cmd_size -> syncpt.get_incr_cmd_size - syncpt.get_sync_ro_map -> syncpt.get_sync_ro_map - sema.get_sema_wait_cmd_size -> sema.get_wait_cmd_size - sema.get_sema_incr_cmd_size -> sema.get_incr_cmd_size - sema.add_sema_cmd -> sema.add_cmd Renamed HAL implementations as: - gk20a_alloc_syncpt_buf -> gk20a_syncpt_alloc_buf - gk20a_free_syncpt_buf -> gk20a_syncpt_free_buf - gk20a_add_syncpt_wait_cmd -> gk20a_syncpt_add_wait_cmd - gk20a_get_syncpt_wait_cmd_size -> gk20a_syncpt_get_wait_cmd_size - gk20a_get_syncpt_incr_per_release -> gk20a_syncpt_get_incr_per_release - gk20a_add_syncpt_incr_cmd -> gk20a_syncpt_add_incr_cmd - gk20a_get_syncpt_incr_cmd_size -> gk20a_syncpt_get_incr_cmd_size - gv11b_alloc_syncpt_buf -> gv11b_syncpt_alloc_buf - gv11b_free_syncpt_buf -> gv11b_syncpt_free_buf - gv11b_add_syncpt_wait_cmd -> gv11b_syncpt_add_wait_cmd - gv11b_get_syncpt_wait_cmd_size -> gv11b_syncpt_get_wait_cmd_size - gv11b_add_syncpt_incr_cmd -> gv11b_syncpt_add_incr_cmd - gv11b_get_syncpt_incr_cmd_size -> gv11b_syncpt_get_incr_cmd_size - gv11b_get_syncpt_incr_per_release -> gv11b_syncpt_get_incr_per_release - gv11b_get_sync_ro_map -> gv11b_syncpt_get_sync_ro_map - gk20a_get_sema_wait_cmd_size -> gk20a_sema_get_wait_cmd_size - gk20a_get_sema_incr_cmd_size -> gk20a_sema_get_incr_cmd_size - gk20a_add_sema_cmd -> gk20a_sema_add_cmd - gv11b_get_sema_wait_cmd_size -> gv11b_sema_get_wait_cmd_size - gv11b_get_sema_incr_cmd_size -> gv11b_sema_get_incr_cmd_size - gv11b_add_sema_cmd -> gv11b_sema_add_cmd Jira NVGPU-1984 Jira NVGPU-1986 Change-Id: I3eb3f669093588df422a82c54fa1ca64788a490c Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2096374 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/*
|
|
* GK20A syncpt cmdbuf
|
|
*
|
|
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <nvgpu/nvgpu_mem.h>
|
|
#include <nvgpu/gk20a.h>
|
|
#include <nvgpu/channel.h>
|
|
|
|
#include "syncpt_cmdbuf_gk20a.h"
|
|
|
|
void gk20a_syncpt_add_wait_cmd(struct gk20a *g,
|
|
struct priv_cmd_entry *cmd, u32 off,
|
|
u32 id, u32 thresh, u64 gpu_va)
|
|
{
|
|
nvgpu_log_fn(g, " ");
|
|
|
|
off = cmd->off + off;
|
|
/* syncpoint_a */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001CU);
|
|
/* payload */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, thresh);
|
|
/* syncpoint_b */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
|
|
/* syncpt_id, switch_en, wait */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x10U);
|
|
}
|
|
|
|
u32 gk20a_syncpt_get_wait_cmd_size(void)
|
|
{
|
|
return 4U;
|
|
}
|
|
|
|
u32 gk20a_syncpt_get_incr_per_release(void)
|
|
{
|
|
return 2U;
|
|
}
|
|
|
|
void gk20a_syncpt_add_incr_cmd(struct gk20a *g,
|
|
bool wfi_cmd, struct priv_cmd_entry *cmd,
|
|
u32 id, u64 gpu_va)
|
|
{
|
|
u32 off = cmd->off;
|
|
|
|
nvgpu_log_fn(g, " ");
|
|
if (wfi_cmd) {
|
|
/* wfi */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001EU);
|
|
/* handle, ignored */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, 0x00000000U);
|
|
}
|
|
/* syncpoint_a */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001CU);
|
|
/* payload, ignored */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, 0U);
|
|
/* syncpoint_b */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
|
|
/* syncpt_id, incr */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x1U);
|
|
/* syncpoint_b */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
|
|
/* syncpt_id, incr */
|
|
nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x1U);
|
|
|
|
}
|
|
|
|
u32 gk20a_syncpt_get_incr_cmd_size(bool wfi_cmd)
|
|
{
|
|
if (wfi_cmd) {
|
|
return 8U;
|
|
} else {
|
|
return 6U;
|
|
}
|
|
}
|
|
|
|
void gk20a_syncpt_free_buf(struct channel_gk20a *c,
|
|
struct nvgpu_mem *syncpt_buf)
|
|
{
|
|
|
|
}
|
|
|
|
int gk20a_syncpt_alloc_buf(struct channel_gk20a *c,
|
|
u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
|
|
{
|
|
return 0;
|
|
}
|