mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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04cd344b35
- During nvgpu module unload, the poweroff sequence will not wait for the ACK from the PMU for the RPCs sent. - Due to this, rpc_payload struct info will be present in pmu seq struct. - This can lead to memory corruption during unload path. - To avoid this, return a different value for driver shutting down scenario from fw ack function and based on this return value free the RPC payload and release the respective pmu sequence struct. Bug 3789998 Change-Id: I25104828d836ae37e127b40c88209da81754ffb8 Signed-off-by: Divya <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2839968 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
237 lines
8.7 KiB
C
237 lines
8.7 KiB
C
/*
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* Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMU_FW_H
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#define NVGPU_PMU_FW_H
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#include <nvgpu/types.h>
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#include <nvgpu/flcnif_cmn.h>
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#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
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struct nvgpu_pmu;
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struct pmu_sequence;
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struct nvgpu_pmu_super_surface;
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struct pmu_pg_cmd;
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struct boardobjgrp;
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struct boardobjgrp_pmu_cmd;
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struct boardobjgrpmask;
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#define PMU_RTOS_UCODE_SIZE_MAX (256U * 1024U)
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#define PMU_RTOS_TRACE_BUFSIZE 0x4000U /* 4K */
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/* Choices for pmu_state */
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#define PMU_FW_STATE_OFF 0U /* PMU is off */
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#define PMU_FW_STATE_STARTING 1U /* PMU is on, but not booted */
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#define PMU_FW_STATE_INIT_RECEIVED 2U /* PMU init message received */
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#define PMU_FW_STATE_ELPG_BOOTING 3U /* PMU is booting */
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#define PMU_FW_STATE_ELPG_BOOTED 4U /* ELPG is initialized */
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#define PMU_FW_STATE_LOADING_PG_BUF 5U /* Loading PG buf */
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#define PMU_FW_STATE_LOADING_ZBC 6U /* Loading ZBC buf */
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#define PMU_FW_STATE_STARTED 7U /* Fully unitialized */
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#define PMU_FW_STATE_EXIT 8U /* Exit PMU state machine */
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/* ACK status for RPCs from PMU firmware */
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/* RPC ACK is recieved from PMU FW */
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#define PMU_FW_ACK_RECEIVED 0
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/*
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* PMU state is OFF so RPC ACK will not be received.
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* Set the ACK status as State OFF
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*/
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#define PMU_FW_ACK_STATE_OFF 1
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/*
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* Driver is shutting down, so we don't wait
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* for ACK from PMU. Set the ACK status to
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* Driver Shutdown
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*/
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#define PMU_FW_ACK_DRIVER_SHUTDOWN 2
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struct pmu_fw_ver_ops {
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u32 (*get_cmd_line_args_size)(struct nvgpu_pmu *pmu);
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void (*set_cmd_line_args_cpu_freq)(struct nvgpu_pmu *pmu,
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u32 freq);
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void (*set_cmd_line_args_trace_size)(struct nvgpu_pmu *pmu,
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u32 size);
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void (*set_cmd_line_args_trace_dma_base)(
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struct nvgpu_pmu *pmu);
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void (*config_cmd_line_args_super_surface)(
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struct nvgpu_pmu *pmu);
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void (*set_cmd_line_args_trace_dma_idx)(
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struct nvgpu_pmu *pmu, u32 idx);
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void * (*get_cmd_line_args_ptr)(struct nvgpu_pmu *pmu);
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void (*set_cmd_line_args_secure_mode)(struct nvgpu_pmu *pmu,
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u8 val);
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u32 (*get_allocation_struct_size)(struct nvgpu_pmu *pmu);
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void (*set_allocation_ptr)(struct nvgpu_pmu *pmu,
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void **pmu_alloc_ptr, void *assign_ptr);
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void (*allocation_set_dmem_size)(struct nvgpu_pmu *pmu,
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void *pmu_alloc_ptr, u16 size);
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u16 (*allocation_get_dmem_size)(struct nvgpu_pmu *pmu,
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void *pmu_alloc_ptr);
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u32 (*allocation_get_dmem_offset)(struct nvgpu_pmu *pmu,
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void *pmu_alloc_ptr);
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u32 * (*allocation_get_dmem_offset_addr)(
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struct nvgpu_pmu *pmu, void *pmu_alloc_ptr);
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void (*allocation_set_dmem_offset)(struct nvgpu_pmu *pmu,
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void *pmu_alloc_ptr, u32 offset);
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void * (*allocation_get_fb_addr)(struct nvgpu_pmu *pmu,
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void *pmu_alloc_ptr);
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u32 (*allocation_get_fb_size)(struct nvgpu_pmu *pmu,
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void *pmu_alloc_ptr);
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void (*get_init_msg_queue_params)(u32 id, void *init_msg,
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u32 *index, u32 *offset, u32 *size);
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void *(*get_init_msg_ptr)(struct pmu_init_msg *init);
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u16 (*get_init_msg_sw_mngd_area_off)(
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union pmu_init_msg_pmu *init_msg);
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u16 (*get_init_msg_sw_mngd_area_size)(
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union pmu_init_msg_pmu *init_msg);
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u32 (*get_perfmon_cmd_start_size)(void);
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int (*get_perfmon_cmd_start_offset_of_var)(
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enum pmu_perfmon_cmd_start_fields field,
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u32 *offset);
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void (*perfmon_start_set_cmd_type)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_start_set_group_id)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_start_set_state_id)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_start_set_flags)(struct pmu_perfmon_cmd *pc,
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u8 value);
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u8 (*perfmon_start_get_flags)(struct pmu_perfmon_cmd *pc);
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u32 (*get_perfmon_cmd_init_size)(void);
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int (*get_perfmon_cmd_init_offset_of_var)(
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enum pmu_perfmon_cmd_start_fields field,
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u32 *offset);
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void (*perfmon_cmd_init_set_sample_buffer)(
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struct pmu_perfmon_cmd *pc, u16 value);
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void (*perfmon_cmd_init_set_dec_cnt)(
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struct pmu_perfmon_cmd *pc, u8 value);
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void (*perfmon_cmd_init_set_base_cnt_id)(
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struct pmu_perfmon_cmd *pc, u8 value);
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void (*perfmon_cmd_init_set_samp_period_us)(
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struct pmu_perfmon_cmd *pc, u32 value);
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void (*perfmon_cmd_init_set_num_cnt)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_cmd_init_set_mov_avg)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void *(*get_seq_in_alloc_ptr)(struct pmu_sequence *seq);
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void *(*get_seq_out_alloc_ptr)(struct pmu_sequence *seq);
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u32 (*get_perfmon_cntr_sz)(struct nvgpu_pmu *pmu);
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void* (*get_perfmon_cntr_ptr)(struct nvgpu_pmu *pmu);
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void (*set_perfmon_cntr_ut)(struct nvgpu_pmu *pmu, u16 ut);
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void (*set_perfmon_cntr_lt)(struct nvgpu_pmu *pmu, u16 lt);
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void (*set_perfmon_cntr_valid)(struct nvgpu_pmu *pmu, u8 val);
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void (*set_perfmon_cntr_index)(struct nvgpu_pmu *pmu, u8 val);
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void (*set_perfmon_cntr_group_id)(struct nvgpu_pmu *pmu,
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u8 gid);
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u8 (*pg_cmd_eng_buf_load_size)(struct pmu_pg_cmd *pg);
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void (*pg_cmd_eng_buf_load_set_cmd_type)(struct pmu_pg_cmd *pg,
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u8 value);
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void (*pg_cmd_eng_buf_load_set_engine_id)(struct pmu_pg_cmd *pg,
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u8 value);
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void (*pg_cmd_eng_buf_load_set_buf_idx)(struct pmu_pg_cmd *pg,
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u8 value);
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void (*pg_cmd_eng_buf_load_set_pad)(struct pmu_pg_cmd *pg,
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u8 value);
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void (*pg_cmd_eng_buf_load_set_buf_size)(struct pmu_pg_cmd *pg,
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u16 value);
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void (*pg_cmd_eng_buf_load_set_dma_base)(struct pmu_pg_cmd *pg,
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u32 value);
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void (*pg_cmd_eng_buf_load_set_dma_offset)(struct pmu_pg_cmd *pg,
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u8 value);
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void (*pg_cmd_eng_buf_load_set_dma_idx)(struct pmu_pg_cmd *pg,
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u8 value);
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struct {
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int (*boardobjgrp_pmucmd_construct_impl)
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(struct gk20a *g,
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struct boardobjgrp *pboardobjgrp,
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struct boardobjgrp_pmu_cmd *cmd, u8 id, u8 msgid,
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u16 hdrsize, u16 entrysize, u16 fbsize, u32 ss_offset,
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u8 rpc_func_id);
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int (*boardobjgrp_pmuset_impl)(struct gk20a *g,
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struct boardobjgrp *pboardobjgrp);
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int (*boardobjgrp_pmugetstatus_impl)(struct gk20a *g,
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struct boardobjgrp *pboardobjgrp,
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struct boardobjgrpmask *mask);
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int (*is_boardobjgrp_pmucmd_id_valid)(struct gk20a *g,
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struct boardobjgrp *pboardobjgrp,
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struct boardobjgrp_pmu_cmd *cmd);
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} obj;
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struct {
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int (*clk_set_boot_clk)(struct gk20a *g);
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} clk;
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int (*prepare_ns_ucode_blob)(struct gk20a *g);
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};
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struct pmu_rtos_fw {
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struct pmu_fw_ver_ops ops;
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struct nvgpu_firmware *fw_desc;
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struct nvgpu_firmware *fw_image;
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struct nvgpu_firmware *fw_sig;
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struct nvgpu_mem ucode;
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struct nvgpu_mem ucode_boot_args;
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struct nvgpu_mem ucode_core_dump;
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u32 state;
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bool ready;
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union {
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struct pmu_cmdline_args_v3 args_v3;
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struct pmu_cmdline_args_v4 args_v4;
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struct pmu_cmdline_args_v5 args_v5;
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struct pmu_cmdline_args_v6 args_v6;
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struct pmu_cmdline_args_v7 args_v7;
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};
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};
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void nvgpu_pmu_fw_get_cmd_line_args_offset(struct gk20a *g,
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u32 *args_offset);
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void nvgpu_pmu_fw_state_change(struct gk20a *g, struct nvgpu_pmu *pmu,
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u32 pmu_state, bool post_change_event);
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u32 nvgpu_pmu_get_fw_state(struct gk20a *g, struct nvgpu_pmu *pmu);
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bool nvgpu_pmu_get_fw_ready(struct gk20a *g, struct nvgpu_pmu *pmu);
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void nvgpu_pmu_set_fw_ready(struct gk20a *g, struct nvgpu_pmu *pmu,
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bool status);
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int nvgpu_pmu_wait_fw_ready(struct gk20a *g, struct nvgpu_pmu *pmu);
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int nvgpu_pmu_wait_fw_ack_status(struct gk20a *g, struct nvgpu_pmu *pmu,
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u32 timeout_ms, void *var, u8 val);
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int nvgpu_pmu_init_fw_ver_ops(struct gk20a *g,
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struct nvgpu_pmu *pmu, u32 app_version);
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struct nvgpu_firmware *nvgpu_pmu_fw_sig_desc(struct gk20a *g,
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struct nvgpu_pmu *pmu);
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struct nvgpu_firmware *nvgpu_pmu_fw_desc_desc(struct gk20a *g,
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struct nvgpu_pmu *pmu);
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struct nvgpu_firmware *nvgpu_pmu_fw_image_desc(struct gk20a *g,
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struct nvgpu_pmu *pmu);
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void nvgpu_pmu_fw_deinit(struct gk20a *g, struct nvgpu_pmu *pmu,
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struct pmu_rtos_fw *rtos_fw);
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int nvgpu_pmu_init_pmu_fw(struct gk20a *g, struct nvgpu_pmu *pmu,
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struct pmu_rtos_fw **rtos_fw_p);
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int nvgpu_pmu_ns_fw_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu);
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#endif /* NVGPU_PMU_FW_H */
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