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9a55ecb5d2
PMU mutexes used by FIFO and runlists is functionality independent of the PMU command and message management. Remove related functionality from pmu_ipc.c and prepare pmu_mutex.c. Prepare PMU HAL unit that contains gk20a specific PMU mutexes handling. JIRA NVGPU-1970 Change-Id: I0204be2ef9d2c000004667af3c18dc527d7ac25f Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2079142 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
112 lines
2.9 KiB
C
112 lines
2.9 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu/mutex.h>
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#include <nvgpu/gk20a.h>
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int nvgpu_pmu_mutexes_alloc(struct gk20a *g, struct pmu_mutexes *mutexes)
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{
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mutexes->cnt = g->ops.pmu.pmu_mutex_size();
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mutexes->mutex = nvgpu_kzalloc(g, mutexes->cnt *
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sizeof(struct pmu_mutex));
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if (mutexes->mutex == NULL) {
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return -ENOMEM;
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}
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return 0;
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}
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void nvgpu_pmu_mutexes_init(struct pmu_mutexes *mutexes)
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{
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u32 i;
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for (i = 0; i < mutexes->cnt; i++) {
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mutexes->mutex[i].id = i;
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mutexes->mutex[i].index = i;
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}
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}
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void nvgpu_pmu_mutexes_free(struct gk20a *g, struct pmu_mutexes *mutexes)
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{
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nvgpu_kfree(g, mutexes->mutex);
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}
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int nvgpu_pmu_mutex_acquire(struct gk20a *g, struct pmu_mutexes *mutexes,
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u32 id, u32 *token)
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{
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struct pmu_mutex *mutex;
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u32 owner;
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int err;
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WARN_ON(token == NULL);
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WARN_ON(!PMU_MUTEX_ID_IS_VALID(id));
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WARN_ON(id > mutexes->cnt);
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mutex = &mutexes->mutex[id];
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owner = g->ops.pmu.pmu_mutex_owner(g, mutexes, id);
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if (*token != PMU_INVALID_MUTEX_OWNER_ID && *token == owner) {
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WARN_ON(mutex->ref_cnt == 0U);
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nvgpu_err(g, "already acquired by owner : 0x%08x", *token);
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mutex->ref_cnt++;
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return 0;
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}
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err = g->ops.pmu.pmu_mutex_acquire(g, mutexes, id, token);
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if (err == 0) {
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mutex->ref_cnt = 1;
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}
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return err;
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}
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int nvgpu_pmu_mutex_release(struct gk20a *g, struct pmu_mutexes *mutexes,
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u32 id, u32 *token)
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{
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struct pmu_mutex *mutex;
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u32 owner;
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WARN_ON(token == NULL);
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WARN_ON(!PMU_MUTEX_ID_IS_VALID(id));
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WARN_ON(id > mutexes->cnt);
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mutex = &mutexes->mutex[id];
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owner = g->ops.pmu.pmu_mutex_owner(g, mutexes, id);
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if (*token != owner) {
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nvgpu_err(g, "requester 0x%08x NOT match owner 0x%08x",
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*token, owner);
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return -EINVAL;
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}
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if (--mutex->ref_cnt > 0U) {
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return -EBUSY;
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}
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g->ops.pmu.pmu_mutex_release(g, mutexes, id, token);
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return 0;
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}
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