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06fd513e1e
nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc APIs. So, move the enum into mc.h, and replace the include of unit.h with mc.h where appropriate. And update the yaml arch. JIRA NVGPU-4144 Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2216106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
155 lines
3.7 KiB
C
155 lines
3.7 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifdef CONFIG_NVGPU_TRACE
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#include <trace/events/gk20a.h>
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#endif
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#include <linux/irqreturn.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/atomic.h>
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#include "os_linux.h"
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irqreturn_t nvgpu_intr_stall(struct gk20a *g)
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{
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u32 mc_intr_0;
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#ifdef CONFIG_NVGPU_TRACE
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trace_mc_gk20a_intr_stall(g->name);
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#endif
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if (nvgpu_is_powered_off(g))
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return IRQ_NONE;
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/* not from gpu when sharing irq with others */
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mc_intr_0 = g->ops.mc.intr_stall(g);
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if (unlikely(!mc_intr_0))
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return IRQ_NONE;
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g->ops.mc.intr_stall_pause(g);
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#ifndef CONFIG_NVGPU_RECOVERY
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if (g->sw_quiesce_pending) {
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return IRQ_NONE;
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}
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#endif
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nvgpu_atomic_inc(&g->hw_irq_stall_count);
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#ifdef CONFIG_NVGPU_TRACE
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trace_mc_gk20a_intr_stall_done(g->name);
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#endif
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return IRQ_WAKE_THREAD;
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}
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irqreturn_t nvgpu_intr_thread_stall(struct gk20a *g)
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{
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int hw_irq_count;
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nvgpu_log(g, gpu_dbg_intr, "interrupt thread launched");
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#ifdef CONFIG_NVGPU_TRACE
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trace_mc_gk20a_intr_thread_stall(g->name);
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#endif
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hw_irq_count = nvgpu_atomic_read(&g->hw_irq_stall_count);
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g->ops.mc.isr_stall(g);
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g->ops.mc.intr_stall_resume(g);
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/* sync handled irq counter before re-enabling interrupts */
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nvgpu_atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
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nvgpu_cond_broadcast(&g->sw_irq_stall_last_handled_cond);
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#ifdef CONFIG_NVGPU_TRACE
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trace_mc_gk20a_intr_thread_stall_done(g->name);
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#endif
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return IRQ_HANDLED;
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}
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irqreturn_t nvgpu_intr_nonstall(struct gk20a *g)
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{
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u32 non_stall_intr_val;
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u32 hw_irq_count;
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int ops_old, ops_new, ops = 0;
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struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
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if (nvgpu_is_powered_off(g))
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return IRQ_NONE;
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/* not from gpu when sharing irq with others */
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non_stall_intr_val = g->ops.mc.intr_nonstall(g);
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if (unlikely(!non_stall_intr_val))
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return IRQ_NONE;
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g->ops.mc.intr_nonstall_pause(g);
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#ifndef CONFIG_NVGPU_RECOVERY
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if (g->sw_quiesce_pending) {
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return IRQ_NONE;
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}
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#endif
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ops = g->ops.mc.isr_nonstall(g);
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if (ops) {
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do {
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ops_old = atomic_read(&l->nonstall_ops);
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ops_new = ops_old | ops;
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} while (ops_old != atomic_cmpxchg(&l->nonstall_ops,
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ops_old, ops_new));
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queue_work(l->nonstall_work_queue, &l->nonstall_fn_work);
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}
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hw_irq_count = nvgpu_atomic_inc_return(&g->hw_irq_nonstall_count);
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/* sync handled irq counter before re-enabling interrupts */
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nvgpu_atomic_set(&g->sw_irq_nonstall_last_handled, hw_irq_count);
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g->ops.mc.intr_nonstall_resume(g);
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nvgpu_cond_broadcast(&g->sw_irq_nonstall_last_handled_cond);
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return IRQ_HANDLED;
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}
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static void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops)
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{
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bool semaphore_wakeup, post_events;
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semaphore_wakeup =
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(((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ?
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true : false);
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post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ?
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true: false);
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if (semaphore_wakeup) {
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g->ops.semaphore_wakeup(g, post_events);
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}
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}
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void nvgpu_intr_nonstall_cb(struct work_struct *work)
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{
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struct nvgpu_os_linux *l =
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container_of(work, struct nvgpu_os_linux, nonstall_fn_work);
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struct gk20a *g = &l->g;
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do {
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u32 ops;
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ops = atomic_xchg(&l->nonstall_ops, 0);
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mc_gk20a_handle_intr_nonstall(g, ops);
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} while (atomic_read(&l->nonstall_ops) != 0);
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}
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