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bcbc87dc2e
Interface header files for PMU features are now moved under PMU header files directory include/nvgpu/pmu. And fix bulk of coding style issues. Update header file names and guards. JIRA NVGPU-1971 Change-Id: Idf53fc09d8928d1b0a1cd16eef886de010dae06b Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2093006 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
110 lines
3.2 KiB
C
110 lines
3.2 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PERF_VFE_VAR_H
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#define NVGPU_PERF_VFE_VAR_H
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#include <nvgpu/boardobjgrp.h>
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#include <nvgpu/boardobjgrp_e32.h>
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#include <nvgpu/boardobjgrp_e255.h>
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#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
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#define VFE_VAR_GET(_pperf, _idx) \
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((struct vfe_var)BOARDOBJGRP_OBJ_GET_BY_IDX( \
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&((_pperf)->vfe.vars.super.super), (_idx)))
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#define VFE_VAR_IDX_IS_VALID(_pperf, _idx) \
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boardobjgrp_idxisvalid(&((_pperf)->vfe.vars.super.super), (_idx))
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struct vfe_var {
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struct boardobj super;
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u32 out_range_min;
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u32 out_range_max;
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struct boardobjgrpmask_e32 mask_dependent_vars;
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struct boardobjgrpmask_e255 mask_dependent_equs;
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bool b_is_dynamic_valid;
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bool b_is_dynamic;
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};
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struct vfe_var_derived {
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struct vfe_var super;
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};
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struct vfe_var_derived_product {
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struct vfe_var_derived super;
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u8 var_idx0;
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u8 var_idx1;
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};
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struct vfe_var_derived_sum {
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struct vfe_var_derived super;
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u8 var_idx0;
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u8 var_idx1;
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};
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struct vfe_var_single {
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struct vfe_var super;
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u8 override_type;
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u32 override_value;
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};
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struct vfe_var_single_frequency {
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struct vfe_var_single super;
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u8 clk_domain_idx;
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};
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struct vfe_var_single_voltage {
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struct vfe_var_single super;
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};
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struct vfe_var_single_caller_specified {
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struct vfe_var_single super;
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u8 uid;
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};
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struct vfe_var_single_sensed {
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struct vfe_var_single super;
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};
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struct vfe_var_single_sensed_fuse {
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struct vfe_var_single_sensed super;
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struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info;
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struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info vfield_info;
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struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info;
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struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_val_default;
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bool b_fuse_value_signed;
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u32 fuse_value_integer;
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u32 fuse_value_hw_integer;
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u8 fuse_version;
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bool b_version_check_done;
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};
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struct vfe_var_single_sensed_temp {
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struct vfe_var_single_sensed super;
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u8 therm_channel_index;
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int temp_hysteresis_positive;
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int temp_hysteresis_negative;
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int temp_default;
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};
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#endif /* NVGPU_PERF_VFE_VAR_H */
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