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git://nv-tegra.nvidia.com/linux-nvgpu.git
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93fd6644f4
Moved below hals from {chip}/fifo_{chip}.[ch] to hal/fifo
get_mmu_fault_info
get_mmu_fault_desc
get_mmu_fault_client_desc
get_mmu_fault_gpc_desc
Moved gk20a_fifo_handle_dropped_mmu_fault to hal/fifo
JIRA NVGPU-1313
Change-Id: I949bcd482156c6e381006387372f13770277e8c5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083287
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/log.h>
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#include <nvgpu/io.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/engines.h>
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#include <hal/fifo/mmu_fault_gp10b.h>
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#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
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/* fault info/descriptions */
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static const char * const gp10b_fault_type_descs[] = {
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"pde", /*fifo_intr_mmu_fault_info_type_pde_v() == 0 */
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"pde size",
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"pte",
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"va limit viol",
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"unbound inst",
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"priv viol",
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"ro viol",
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"wo viol",
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"pitch mask",
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"work creation",
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"bad aperture",
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"compression failure",
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"bad kind",
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"region viol",
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"dual ptes",
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"poisoned",
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"atomic violation",
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};
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static const char * const gp10b_hub_client_descs[] = {
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"vip", "ce0", "ce1", "dniso", "fe", "fecs", "host", "host cpu",
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"host cpu nb", "iso", "mmu", "mspdec", "msppp", "msvld",
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"niso", "p2p", "pd", "perf", "pmu", "raster twod", "scc",
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"scc nb", "sec", "ssync", "gr copy", "xv", "mmu nb",
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"msenc", "d falcon", "sked", "a falcon", "n/a",
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"hsce0", "hsce1", "hsce2", "hsce3", "hsce4", "hsce5",
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"hsce6", "hsce7", "hsce8", "hsce9", "hshub",
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"ptp x0", "ptp x1", "ptp x2", "ptp x3", "ptp x4",
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"ptp x5", "ptp x6", "ptp x7", "vpr scrubber0", "vpr scrubber1",
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};
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/* fill in mmu fault desc */
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void gp10b_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmufault)
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{
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if (mmufault->fault_type >= ARRAY_SIZE(gp10b_fault_type_descs)) {
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WARN_ON(mmufault->fault_type >=
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ARRAY_SIZE(gp10b_fault_type_descs));
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} else {
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mmufault->fault_type_desc =
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gp10b_fault_type_descs[mmufault->fault_type];
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}
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}
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/* fill in mmu fault client description */
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void gp10b_fifo_get_mmu_fault_client_desc(struct mmu_fault_info *mmufault)
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{
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if (mmufault->client_id >= ARRAY_SIZE(gp10b_hub_client_descs)) {
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WARN_ON(mmufault->client_id >=
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ARRAY_SIZE(gp10b_hub_client_descs));
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} else {
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mmufault->client_id_desc =
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gp10b_hub_client_descs[mmufault->client_id];
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}
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}
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void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
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struct mmu_fault_info *mmufault)
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{
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u32 fault_info;
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u32 addr_lo, addr_hi;
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nvgpu_log_fn(g, "mmu_fault_id %d", mmu_fault_id);
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(void) memset(mmufault, 0, sizeof(*mmufault));
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fault_info = nvgpu_readl(g,
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fifo_intr_mmu_fault_info_r(mmu_fault_id));
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mmufault->fault_type =
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fifo_intr_mmu_fault_info_type_v(fault_info);
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mmufault->access_type =
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fifo_intr_mmu_fault_info_access_type_v(fault_info);
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mmufault->client_type =
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fifo_intr_mmu_fault_info_client_type_v(fault_info);
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mmufault->client_id =
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fifo_intr_mmu_fault_info_client_v(fault_info);
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addr_lo = nvgpu_readl(g, fifo_intr_mmu_fault_lo_r(mmu_fault_id));
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addr_hi = nvgpu_readl(g, fifo_intr_mmu_fault_hi_r(mmu_fault_id));
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mmufault->fault_addr = hi32_lo32_to_u64(addr_hi, addr_lo);
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/* note:ignoring aperture */
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mmufault->inst_ptr = fifo_intr_mmu_fault_inst_ptr_v(
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nvgpu_readl(g, fifo_intr_mmu_fault_inst_r(mmu_fault_id)));
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/* note: inst_ptr is a 40b phys addr. */
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mmufault->inst_ptr <<= fifo_intr_mmu_fault_inst_ptr_align_shift_v();
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}
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