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4ef4939797
Added the following HALs - ramin.base_shift - ramin.alloc_base Use above HALs in mm, instead of using hw definitions. Defined nvgpu_inst_block_ptr to - get inst_block address, - shift if by base_shift - assert upper 32 bits are 0 - return lower 32 bits Added missing #include for <nvgpu/mm.h> Jira NVGPU-3015 Change-Id: I558a6f4c9fbc6873a5b71f1557ea9ad8eae2778f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2077840 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
40 lines
1.6 KiB
C
40 lines
1.6 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_RAMIN_GK20A_H
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#define NVGPU_RAMIN_GK20A_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_mem;
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void gk20a_ramin_set_gr_ptr(struct gk20a *g,
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struct nvgpu_mem *inst_block, u64 gpu_va);
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void gk20a_ramin_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block,
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u64 pdb_addr, struct nvgpu_mem *pdb_mem);
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void gk20a_ramin_set_adr_limit(struct gk20a *g,
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struct nvgpu_mem *inst_block, u64 va_limit);
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u32 gk20a_ramin_base_shift(void);
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u32 gk20a_ramin_alloc_size(void);
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#endif /* NVGPU_RAMIN_GK20A_H */
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