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4c4f45e7eb
Rule 8.6 Rule 16.4 Rule 10.3 Rule 10.7 JIRA NVGPU-3382 Change-Id: Ie5a8bfefaabd351428745fa95a90f1aac91b1b55 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2111576 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
61 lines
2.4 KiB
C
61 lines
2.4 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_MC_GM20B_H
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#define NVGPU_MC_GM20B_H
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#include <nvgpu/types.h>
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#define MC_ENABLE_DELAY_US 20U
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#define MC_RESET_DELAY_US 20U
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#define MC_RESET_CE_DELAY_US 500U
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struct gk20a;
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enum nvgpu_unit;
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void gm20b_mc_intr_mask(struct gk20a *g);
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void gm20b_mc_intr_enable(struct gk20a *g);
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void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable,
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bool is_stalling, u32 mask);
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void gm20b_mc_isr_stall(struct gk20a *g);
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u32 gm20b_mc_intr_stall(struct gk20a *g);
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void gm20b_mc_intr_stall_pause(struct gk20a *g);
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void gm20b_mc_intr_stall_resume(struct gk20a *g);
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u32 gm20b_mc_intr_nonstall(struct gk20a *g);
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u32 gm20b_mc_isr_nonstall(struct gk20a *g);
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void gm20b_mc_intr_nonstall_pause(struct gk20a *g);
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void gm20b_mc_intr_nonstall_resume(struct gk20a *g);
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void gm20b_mc_enable(struct gk20a *g, u32 units);
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void gm20b_mc_disable(struct gk20a *g, u32 units);
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void gm20b_mc_reset(struct gk20a *g, u32 units);
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bool gm20b_mc_is_intr1_pending(struct gk20a *g,
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enum nvgpu_unit unit, u32 mc_intr_1);
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void gm20b_mc_log_pending_intrs(struct gk20a *g);
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u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
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bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit);
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void gm20b_mc_fb_reset(struct gk20a *g);
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void gm20b_mc_ltc_isr(struct gk20a *g);
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bool gm20b_mc_is_mmu_fault_pending(struct gk20a *g);
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#endif /* NVGPU_MC_GM20B_H */
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