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6c2c4181ae
There are many miscellaneous HALs for various MM related functionality. This patch aims to migrate all the remaining MM code from the <chip>/ mm_<chip>.[ch] files in HAL files under hal/. Much of this is fairly straightforward copy/paste and updates to the HAL init files. The exception to that is the move of the left over gv11b MMU fault handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in a subsequent patch. JIRA NVGPU-2042 Change-Id: I12896de865d890a61afbcb71159cff486119ffb8 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109050 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
70 lines
2.2 KiB
C
70 lines
2.2 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/vm.h>
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#include "mm_gp10b.h"
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int gp10b_mm_init_bar2_vm(struct gk20a *g)
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{
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int err;
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struct mm_gk20a *mm = &g->mm;
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struct nvgpu_mem *inst_block = &mm->bar2.inst_block;
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u32 big_page_size = g->ops.mm.gmmu.get_default_big_page_size();
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/* BAR2 aperture size is 32MB */
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mm->bar2.aperture_size = U32(32) << 20U;
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nvgpu_log_info(g, "bar2 vm size = 0x%x", mm->bar2.aperture_size);
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mm->bar2.vm = nvgpu_vm_init(g, big_page_size, SZ_4K,
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mm->bar2.aperture_size - SZ_4K,
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mm->bar2.aperture_size, false, false, false, "bar2");
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if (mm->bar2.vm == NULL) {
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return -ENOMEM;
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}
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/* allocate instance mem for bar2 */
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err = nvgpu_alloc_inst_block(g, inst_block);
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if (err != 0) {
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goto clean_up_va;
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}
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g->ops.mm.init_inst_block(inst_block, mm->bar2.vm, big_page_size);
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return 0;
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clean_up_va:
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nvgpu_vm_put(mm->bar2.vm);
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return err;
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}
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void gp10b_mm_remove_bar2_vm(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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nvgpu_free_inst_block(g, &mm->bar2.inst_block);
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nvgpu_vm_put(mm->bar2.vm);
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}
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