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Enable logging and error reporting for MIF, DLPL, and TLC blocks. Configure the NVLIPT and IOCTRL interrupt registers to rollup the MIF and TLC errors on the link-specific fatal line and the DLPL interrupts on link-specific intr_a(fatal) line. Both link_err_fatal and link_intr_a are rolled up to stall interrupt line. In the handling ISR, clear the interrupt status registers and print an error. Move the interrupt handling HAL code to /common/hal. JIRA NVGPU-4350 JIRA NVGPU-4351 JIRA NVGPU-5231 JIRA NVGPU-4354 JIRA NVGPU-4355 JIRA NVGPU-4356 Change-Id: I14812499caf506592f3ae84d6681d857730d31ff Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313221 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>