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6eef1a486c
Add unit tests to cover the invalid falcon port access, falcon sw init switch cases, nvgpu_falcon_set_irq, nvgpu_timeout_init failure branch coverage. Compile out the functions nvgpu_falcon_get_mem_size & falcon_bootstrap as they are needed by LS PMU and VBIOS code. For iGPU safety the falcon functions needing these will call the HAL APIs directly. This way we avoid the unreachable code as well. Updated the prototype of falcon bootstrap HAL API as that doesn't return any error. With these changes, we get 100% line coverage for common.falcon unit. JIRA NVGPU-2214 Change-Id: I1fe653d97c1a6a1521d7da38f171928dda58c5b5 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2258311 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
100 lines
3.7 KiB
C
100 lines
3.7 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FALCON_GK20A_H
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#define NVGPU_FALCON_GK20A_H
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#include <nvgpu/falcon.h>
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/* Falcon Register index */
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#define FALCON_REG_R0 (0U)
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#define FALCON_REG_R1 (1U)
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#define FALCON_REG_R2 (2U)
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#define FALCON_REG_R3 (3U)
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#define FALCON_REG_R4 (4U)
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#define FALCON_REG_R5 (5U)
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#define FALCON_REG_R6 (6U)
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#define FALCON_REG_R7 (7U)
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#define FALCON_REG_R8 (8U)
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#define FALCON_REG_R9 (9U)
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#define FALCON_REG_R10 (10U)
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#define FALCON_REG_R11 (11U)
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#define FALCON_REG_R12 (12U)
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#define FALCON_REG_R13 (13U)
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#define FALCON_REG_R14 (14U)
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#define FALCON_REG_R15 (15U)
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#define FALCON_REG_IV0 (16U)
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#define FALCON_REG_IV1 (17U)
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#define FALCON_REG_UNDEFINED (18U)
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#define FALCON_REG_EV (19U)
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#define FALCON_REG_SP (20U)
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#define FALCON_REG_PC (21U)
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#define FALCON_REG_IMB (22U)
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#define FALCON_REG_DMB (23U)
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#define FALCON_REG_CSW (24U)
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#define FALCON_REG_CCR (25U)
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#define FALCON_REG_SEC (26U)
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#define FALCON_REG_CTX (27U)
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#define FALCON_REG_EXCI (28U)
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#define FALCON_REG_RSVD0 (29U)
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#define FALCON_REG_RSVD1 (30U)
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#define FALCON_REG_RSVD2 (31U)
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#define FALCON_REG_SIZE (32U)
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#define FALCON_DMEM_BLKSIZE2 8U
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void gk20a_falcon_reset(struct nvgpu_falcon *flcn);
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bool gk20a_is_falcon_cpu_halted(struct nvgpu_falcon *flcn);
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bool gk20a_is_falcon_idle(struct nvgpu_falcon *flcn);
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bool gk20a_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn);
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u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn,
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enum falcon_mem_type mem_type);
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u8 gk20a_falcon_get_ports_count(struct nvgpu_falcon *flcn,
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enum falcon_mem_type mem_type);
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int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
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u32 dst, u8 *src, u32 size, u8 port);
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int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst,
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u8 *src, u32 size, u8 port, bool sec, u32 tag);
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void gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn,
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u32 boot_vector);
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u32 gk20a_falcon_mailbox_read(struct nvgpu_falcon *flcn,
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u32 mailbox_index);
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void gk20a_falcon_mailbox_write(struct nvgpu_falcon *flcn,
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u32 mailbox_index, u32 data);
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void gk20a_falcon_set_irq(struct nvgpu_falcon *flcn, bool enable,
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u32 intr_mask, u32 intr_dest);
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#ifdef CONFIG_NVGPU_FALCON_DEBUG
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void gk20a_falcon_dump_stats(struct nvgpu_falcon *flcn);
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#endif
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#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
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bool gk20a_falcon_clear_halt_interrupt_status(struct nvgpu_falcon *flcn);
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int gk20a_falcon_copy_from_dmem(struct nvgpu_falcon *flcn,
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u32 src, u8 *dst, u32 size, u8 port);
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int gk20a_falcon_copy_from_imem(struct nvgpu_falcon *flcn, u32 src,
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u8 *dst, u32 size, u8 port);
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void gk20a_falcon_get_ctls(struct nvgpu_falcon *flcn, u32 *sctl,
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u32 *cpuctl);
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#endif
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#endif /* NVGPU_FALCON_GK20A_H */
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