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406913dc42
Currently, size of zbc index table is defined as a macro. This macro is independent of the number of address bits in the ltc zbc index register. Adding below hal will update zbc index table size as per number of address bits. Add hal to get gr_zbc_index_table_size: u32 (*zbc_table_size)(struct gk20a *g); ZBC index table address 0 is reserved. Logic to start zbc table index from 1 is moved to corresponding hals. JIRA NVGPU-4838 Change-Id: I700cadfdd1f3dc5f323055b8f44d769d6627920a Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288479 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
110 lines
3.6 KiB
C
110 lines
3.6 KiB
C
/*
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* GV11B LTC
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*
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* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/gr/zbc.h>
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#include "ltc_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_ltc_gv11b.h>
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#include <nvgpu/utils.h>
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#ifdef CONFIG_NVGPU_GRAPHICS
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/*
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* Sets the ZBC stencil for the passed index.
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*/
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void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
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u32 stencil_depth,
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u32 index)
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{
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nvgpu_writel_check(g, ltc_ltcs_ltss_dstg_zbc_index_r(),
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ltc_ltcs_ltss_dstg_zbc_index_address_f(
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nvgpu_safe_add_u32(index, NVGPU_GR_ZBC_STARTOF_TABLE)));
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nvgpu_writel_check(g,
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ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(),
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stencil_depth);
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}
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#endif /* CONFIG_NVGPU_GRAPHICS */
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#ifdef CONFIG_NVGPU_INJECT_HWERR
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void gv11b_ltc_inject_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info)
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{
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u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
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u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
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u32 ltc = (error_info & 0xFF00U) >> 8U;
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u32 lts = (error_info & 0xFFU);
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u32 reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
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nvgpu_safe_add_u32(nvgpu_safe_mult_u32(ltc, ltc_stride),
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nvgpu_safe_mult_u32(lts, lts_stride)));
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nvgpu_info(g, "Injecting LTC fault %s for ltc: %d, lts: %d",
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err->name, ltc, lts);
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nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
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}
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static inline u32 ltc0_lts0_l1_cache_ecc_control_r(void)
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{
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return ltc_ltc0_lts0_l1_cache_ecc_control_r();
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}
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static inline u32 ltc0_lts0_l1_cache_ecc_control_inject_corrected_err_f(u32 v)
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{
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return ltc_ltc0_lts0_l1_cache_ecc_control_inject_corrected_err_f(v);
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}
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static inline u32 ltc0_lts0_l1_cache_ecc_control_inject_uncorrected_err_f(u32 v)
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{
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return ltc_ltc0_lts0_l1_cache_ecc_control_inject_uncorrected_err_f(v);
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}
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static struct nvgpu_hw_err_inject_info ltc_ecc_err_desc[] = {
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NVGPU_ECC_ERR("cache_rstg_ecc_corrected",
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gv11b_ltc_inject_ecc_error,
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ltc0_lts0_l1_cache_ecc_control_r,
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ltc0_lts0_l1_cache_ecc_control_inject_corrected_err_f),
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NVGPU_ECC_ERR("cache_rstg_ecc_uncorrected",
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gv11b_ltc_inject_ecc_error,
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ltc0_lts0_l1_cache_ecc_control_r,
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ltc0_lts0_l1_cache_ecc_control_inject_uncorrected_err_f),
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};
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static struct nvgpu_hw_err_inject_info_desc ltc_err_desc;
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struct nvgpu_hw_err_inject_info_desc *gv11b_ltc_get_err_desc(struct gk20a *g)
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{
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ltc_err_desc.info_ptr = ltc_ecc_err_desc;
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ltc_err_desc.info_size = nvgpu_safe_cast_u64_to_u32(
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sizeof(ltc_ecc_err_desc) /
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sizeof(struct nvgpu_hw_err_inject_info));
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return <c_err_desc;
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}
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#endif /* CONFIG_NVGPU_INJECT_HWERR */
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