Peter Daifuku 4758f98679 gpu: nvgpu: save req_nr in clk_arb_worker_enqueue ...

In clk_arb_worker_enqueue, save the previous value
of the request counter req_nr, to allow checking
when it has advanced.

JIRA ESRM-398

Change-Id: I9dc90d259a2b415ab84145eeb9406a05e8207b4c
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917558
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2018-10-12 17:35:10 +05:30

..

clk_arb.c

gpu: nvgpu: save req_nr in clk_arb_worker_enqueue

2018-10-12 17:35:10 +05:30

clk_domain.c

gpu: nvgpu: clk: fix MISRA Rule 10.4 Violations

2018-10-12 17:35:09 +05:30

clk_domain.h

nvgpu: clk: MISRA Rule 21.2 header guard fixes

2018-09-13 23:45:22 -07:00

clk_fll.c

gpu: nvgpu: clk: fix MISRA Rule 10.4 Violations

2018-10-12 17:35:09 +05:30

clk_fll.h

nvgpu: clk: MISRA Rule 21.2 header guard fixes

2018-09-13 23:45:22 -07:00

clk_freq_controller.c

gpu: nvgpu: clk: fix MISRA Rule 10.4 Violations

2018-10-12 17:35:09 +05:30

clk_freq_controller.h

gpu: nvgpu: clk: fix MISRA Rule 10.4 Violations

2018-10-12 17:35:09 +05:30

clk_mclk.h

nvgpu: clk: MISRA Rule 21.2 header guard fixes

2018-09-13 23:45:22 -07:00

clk_prog.c

gpu: nvgpu: clk: fix MISRA Rule 10.4 Violations

2018-10-12 17:35:09 +05:30

clk_prog.h

nvgpu: clk: MISRA Rule 21.2 header guard fixes

2018-09-13 23:45:22 -07:00

clk_vf_point.c

gpu: nvgpu: change location of gk20a.h

2018-09-14 15:34:58 -07:00

clk_vf_point.h

nvgpu: clk: MISRA Rule 21.2 header guard fixes

2018-09-13 23:45:22 -07:00

clk_vin.c

gpu: nvgpu: clk: fix MISRA Rule 10.4 Violations

2018-10-12 17:35:09 +05:30

clk_vin.h

nvgpu: clk: MISRA Rule 21.2 header guard fixes

2018-09-13 23:45:22 -07:00

clk.c

gpu: nvgpu: clk: fix MISRA Rule 10.4 Violations

2018-10-12 17:35:09 +05:30

clk.h

gpu: nvgpu: clk: fix MISRA Rule 10.4 Violations

2018-10-12 17:35:09 +05:30