Mahantesh Kumbar bbf70e1ce9 gpu: nvgpu: Bootstrap SEC2 RTOS & LS falcons ...

-Call secured_sec2_start() to start SEC2 RTOS ucode execution
 on SEC2 falcon in nvgpu_init_sec2_support() function
-Modified nvgpu_init_pmu_support() to do PMU bootstrap
 from SEC2 RTOS by sending command.
-Added function nvgpu_sec2_bootstrap_ls_falcons() to
 bootstrap LS falcon by taking falcon id as a parameter &
 sending request to SEC2 RTOS with command
 NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON.
-Modified method gr_gm20b_load_ctxsw_ucode() to
 bootstrap FECS & GPCCS falcons using SEC2 RTOS
 in cold boot & recovery path.
-Updated ldr_cfg parameters for SEC2 falcon
-Skip adding PMU ucode details to non-wpr blob preparation
 to skip supporting of LS PMU falcon bootstrap.

JIRA NVGPUT-85

Change-Id: I5f6828e2737e247767814014801671327bb34a4e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832363
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2018-10-12 17:35:08 +05:30

..

sec2_ipc.c

gpu: nvgpu: SEC2 IPC support

2018-10-12 17:35:08 +05:30

sec2.c

gpu: nvgpu: Bootstrap SEC2 RTOS & LS falcons

2018-10-12 17:35:08 +05:30