Seshendra Gadagottu 0f1726ae1f gpu: nvgpu: support for non-secure/secure ctxsw loading ...

Code for secure/non-secure ctxsw booting spread across gr_gk20a.c
and gr_gm20b.c. With this change this code is move to gr falcon unit.

Ctxsw loading is now supported with 2 supported common functions:
1.Non secure boot:
 int nvgpu_gr_falcon_load_ctxsw_ucode(struct gk20a *g);
2.Secure boot:
int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g);

Now gr ops function "int (*load_ctxsw_ucode)(struct gk20a *g);" is moved to
gr falcon ops and in chip hals it is set with secure/non-secure booting.

Non-secure booting: nvgpu_gr_falcon_load_ctxsw_ucode support ctxsw loading
in 2 methods: bit-banging uode or booting with bootloader

A. Common and hal functions for non-secure bit-banging ctxsw loading:
Common: static void nvgpu_gr_falcon_load_dmem(struct gk20a *g) ->
Hals: void (*load_gpccs_dmem)(struct gk20a *g,i
			 const u32 *ucode_u32_data, u32 size);
      void (*load_fecs_dmem)(struct gk20a *g,
			const u32 *ucode_u32_data, u32 size);
Common: static void nvgpu_gr_falcon_load_imem(struct gk20a *g) ->
Hals:  void (*load_gpccs_imem)(struct gk20a *g,
			 const u32 *ucode_u32_data, u32 size);
       void (*load_fecs_imem)(struct gk20a *g,
			const u32 *ucode_u32_data, u32 size);
Other basic HALs:
void (*configure_fmodel)(struct gk20a *g); -> configure fmodel for ctxsw loading
void (*start_ucode)(struct gk20a *g);  -> start running ctxcw ucode

B.Common and hal functions for non-secure ctxsw loading with bootloader
First get the ctxsw ucode using: nvgpu_gr_falcon_init_ctxsw_ucode, then
Common: static void nvgpu_gr_falcon_load_with_bootloader(struct gk20a *g)
        void nvgpu_gr_falcon_bind_instblk((struct gk20a *g) ->
Hal: void (*bind_instblk)(struct gk20a *g, struct nvgpu_mem *mem, u64 inst_ptr);

Common: nvgpu_gr_falcon_load_ctxsw_ucode_segments ->
		nvgpu_gr_falcon_load_ctxsw_ucode_header ->
		nvgpu_gr_falcon_load_ctxsw_ucode_boot for both fecs and gpccs ->
Hals: void (*load_ctxsw_ucode_header)(struct gk20a *g, u32 reg_offset,
	u32 boot_signature, u32 addr_code32, u32 addr_data32,
	u32 code_size, u32 data_size);
void (*load_ctxsw_ucode_boot)(struct gk20a *g, u64 reg_offset, u32 boot_entry,
	u32 addr_load32, u32 blocks, u32 dst);
Other basic HAL to get gpccs start offset:
  u32 (*get_gpccs_start_reg_offset)(void);

C.Secure booting is support with gpmu and acr and with following additional
common function in gr falcon.
static void nvgpu_gr_falcon_load_gpccs_with_bootloader(struct gk20a *g) ->
  nvgpu_gr_falcon_bind_instblk and  nvgpu_gr_falcon_load_ctxsw_ucode_segments
Additional basic hals:
void (*start_gpccs)(struct gk20a *g);
void (*start_fecs)(struct gk20a *g);

Following ops from gr is removed, since it is not required to set by chip hals:
void (*falcon_load_ucode)(struct gk20a *g, u64 addr_base,
	struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset);

Now this is handled by static common function:
static int nvgpu_gr_falcon_copy_ctxsw_ucode_segments( struct gk20a *g,
	struct nvgpu_mem *dst, struct gk20a_ctxsw_ucode_segments *segments,
	u32 *bootimage, u32 *code, u32 *data)

JIRA NVGPU-1881

Change-Id: I895a03faaf1a21286316befde24765c8b55075cf
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083388
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-03-29 01:15:50 -07:00

..

nvgpu

gpu: nvgpu: support for non-secure/secure ctxsw loading

2019-03-29 01:15:50 -07:00

Makefile

nvgpu: use kernel overlay features

2017-10-29 11:00:55 -07:00