mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals or casting operands to have same type of operands when an arithmetic operation is performed. This fixes violations where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1921459 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
370 lines
10 KiB
C
370 lines
10 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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static void nvgpu_ecc_stat_add(struct gk20a *g, struct nvgpu_ecc_stat *stat)
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{
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struct nvgpu_ecc *ecc = &g->ecc;
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nvgpu_init_list_node(&stat->node);
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nvgpu_list_add_tail(&stat->node, &ecc->stats_list);
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ecc->stats_count++;
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}
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static void nvgpu_ecc_init(struct gk20a *g)
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{
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struct nvgpu_ecc *ecc = &g->ecc;
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nvgpu_init_list_node(&ecc->stats_list);
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}
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int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
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struct nvgpu_ecc_stat ***stat, const char *name)
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{
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struct gr_gk20a *gr = &g->gr;
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struct nvgpu_ecc_stat **stats;
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u32 gpc, tpc;
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int err = 0;
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stats = nvgpu_kzalloc(g, sizeof(*stats) * gr->gpc_count);
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if (stats == NULL) {
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return -ENOMEM;
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}
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for (gpc = 0; gpc < gr->gpc_count; gpc++) {
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stats[gpc] = nvgpu_kzalloc(g,
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sizeof(*stats[gpc]) * gr->gpc_tpc_count[gpc]);
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if (stats[gpc] == NULL) {
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err = -ENOMEM;
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break;
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}
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}
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if (err != 0) {
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while (gpc-- != 0u) {
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nvgpu_kfree(g, stats[gpc]);
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}
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nvgpu_kfree(g, stats);
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return err;
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}
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for (gpc = 0; gpc < gr->gpc_count; gpc++) {
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for (tpc = 0; tpc < gr->gpc_tpc_count[gpc]; tpc++) {
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(void) snprintf(stats[gpc][tpc].name,
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NVGPU_ECC_STAT_NAME_MAX_SIZE,
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"gpc%d_tpc%d_%s", gpc, tpc, name);
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nvgpu_ecc_stat_add(g, &stats[gpc][tpc]);
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}
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}
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*stat = stats;
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return 0;
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}
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int nvgpu_ecc_counter_init_per_gpc(struct gk20a *g,
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struct nvgpu_ecc_stat **stat, const char *name)
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{
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struct gr_gk20a *gr = &g->gr;
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struct nvgpu_ecc_stat *stats;
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u32 gpc;
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stats = nvgpu_kzalloc(g, sizeof(*stats) * gr->gpc_count);
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if (stats == NULL) {
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return -ENOMEM;
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}
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for (gpc = 0; gpc < gr->gpc_count; gpc++) {
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(void) snprintf(stats[gpc].name, NVGPU_ECC_STAT_NAME_MAX_SIZE,
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"gpc%d_%s", gpc, name);
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nvgpu_ecc_stat_add(g, &stats[gpc]);
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}
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*stat = stats;
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return 0;
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}
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int nvgpu_ecc_counter_init(struct gk20a *g,
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struct nvgpu_ecc_stat **stat, const char *name)
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{
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struct nvgpu_ecc_stat *stats;
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stats = nvgpu_kzalloc(g, sizeof(*stats));
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if (stats == NULL) {
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return -ENOMEM;
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}
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(void)strncpy(stats->name, name, NVGPU_ECC_STAT_NAME_MAX_SIZE - 1);
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nvgpu_ecc_stat_add(g, stats);
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*stat = stats;
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return 0;
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}
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int nvgpu_ecc_counter_init_per_lts(struct gk20a *g,
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struct nvgpu_ecc_stat ***stat, const char *name)
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{
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struct gr_gk20a *gr = &g->gr;
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struct nvgpu_ecc_stat **stats;
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u32 ltc, lts;
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int err = 0;
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stats = nvgpu_kzalloc(g, sizeof(*stats) * g->ltc_count);
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if (stats == NULL) {
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return -ENOMEM;
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}
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for (ltc = 0; ltc < g->ltc_count; ltc++) {
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stats[ltc] = nvgpu_kzalloc(g,
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sizeof(*stats[ltc]) * gr->slices_per_ltc);
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if (stats[ltc] == NULL) {
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err = -ENOMEM;
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break;
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}
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}
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if (err != 0) {
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while (ltc-- > 0u) {
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nvgpu_kfree(g, stats[ltc]);
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}
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nvgpu_kfree(g, stats);
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return err;
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}
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for (ltc = 0; ltc < g->ltc_count; ltc++) {
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for (lts = 0; lts < gr->slices_per_ltc; lts++) {
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(void) snprintf(stats[ltc][lts].name,
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NVGPU_ECC_STAT_NAME_MAX_SIZE,
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"ltc%d_lts%d_%s", ltc, lts, name);
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nvgpu_ecc_stat_add(g, &stats[ltc][lts]);
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}
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}
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*stat = stats;
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return 0;
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}
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int nvgpu_ecc_counter_init_per_fbpa(struct gk20a *g,
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struct nvgpu_ecc_stat **stat, const char *name)
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{
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int i;
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int num_fbpa = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS);
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struct nvgpu_ecc_stat *stats;
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stats = nvgpu_kzalloc(g, sizeof(*stats) * (size_t)num_fbpa);
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if (stats == NULL) {
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return -ENOMEM;
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}
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for (i = 0; i < num_fbpa; i++) {
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(void) snprintf(stats[i].name, NVGPU_ECC_STAT_NAME_MAX_SIZE,
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"fbpa%d_%s", i, name);
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nvgpu_ecc_stat_add(g, &stats[i]);
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}
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*stat = stats;
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return 0;
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}
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/* release all ecc_stat */
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void nvgpu_ecc_free(struct gk20a *g)
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{
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struct nvgpu_ecc *ecc = &g->ecc;
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struct gr_gk20a *gr = &g->gr;
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u32 i;
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for (i = 0; i < gr->gpc_count; i++) {
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if (ecc->gr.sm_lrf_ecc_single_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_lrf_ecc_single_err_count[i]);
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}
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if (ecc->gr.sm_lrf_ecc_double_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_lrf_ecc_double_err_count[i]);
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}
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if (ecc->gr.sm_shm_ecc_sec_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_shm_ecc_sec_count[i]);
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}
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if (ecc->gr.sm_shm_ecc_sed_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_shm_ecc_sed_count[i]);
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}
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if (ecc->gr.sm_shm_ecc_ded_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_shm_ecc_ded_count[i]);
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}
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if (ecc->gr.tex_ecc_total_sec_pipe0_count != NULL) {
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nvgpu_kfree(g, ecc->gr.tex_ecc_total_sec_pipe0_count[i]);
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}
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if (ecc->gr.tex_ecc_total_ded_pipe0_count != NULL) {
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nvgpu_kfree(g, ecc->gr.tex_ecc_total_ded_pipe0_count[i]);
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}
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if (ecc->gr.tex_unique_ecc_sec_pipe0_count != NULL) {
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nvgpu_kfree(g, ecc->gr.tex_unique_ecc_sec_pipe0_count[i]);
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}
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if (ecc->gr.tex_unique_ecc_ded_pipe0_count != NULL) {
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nvgpu_kfree(g, ecc->gr.tex_unique_ecc_ded_pipe0_count[i]);
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}
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if (ecc->gr.tex_ecc_total_sec_pipe1_count != NULL) {
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nvgpu_kfree(g, ecc->gr.tex_ecc_total_sec_pipe1_count[i]);
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}
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if (ecc->gr.tex_ecc_total_ded_pipe1_count != NULL) {
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nvgpu_kfree(g, ecc->gr.tex_ecc_total_ded_pipe1_count[i]);
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}
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if (ecc->gr.tex_unique_ecc_sec_pipe1_count != NULL) {
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nvgpu_kfree(g, ecc->gr.tex_unique_ecc_sec_pipe1_count[i]);
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}
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if (ecc->gr.tex_unique_ecc_ded_pipe1_count != NULL) {
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nvgpu_kfree(g, ecc->gr.tex_unique_ecc_ded_pipe1_count[i]);
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}
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if (ecc->gr.sm_l1_tag_ecc_corrected_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_l1_tag_ecc_corrected_err_count[i]);
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}
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if (ecc->gr.sm_l1_tag_ecc_uncorrected_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_l1_tag_ecc_uncorrected_err_count[i]);
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}
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if (ecc->gr.sm_cbu_ecc_corrected_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_cbu_ecc_corrected_err_count[i]);
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}
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if (ecc->gr.sm_cbu_ecc_uncorrected_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_cbu_ecc_uncorrected_err_count[i]);
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}
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if (ecc->gr.sm_l1_data_ecc_corrected_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_l1_data_ecc_corrected_err_count[i]);
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}
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if (ecc->gr.sm_l1_data_ecc_uncorrected_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_l1_data_ecc_uncorrected_err_count[i]);
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}
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if (ecc->gr.sm_icache_ecc_corrected_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_icache_ecc_corrected_err_count[i]);
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}
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if (ecc->gr.sm_icache_ecc_uncorrected_err_count != NULL) {
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nvgpu_kfree(g, ecc->gr.sm_icache_ecc_uncorrected_err_count[i]);
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}
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}
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nvgpu_kfree(g, ecc->gr.sm_lrf_ecc_single_err_count);
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nvgpu_kfree(g, ecc->gr.sm_lrf_ecc_double_err_count);
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nvgpu_kfree(g, ecc->gr.sm_shm_ecc_sec_count);
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nvgpu_kfree(g, ecc->gr.sm_shm_ecc_sed_count);
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nvgpu_kfree(g, ecc->gr.sm_shm_ecc_ded_count);
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nvgpu_kfree(g, ecc->gr.tex_ecc_total_sec_pipe0_count);
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nvgpu_kfree(g, ecc->gr.tex_ecc_total_ded_pipe0_count);
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nvgpu_kfree(g, ecc->gr.tex_unique_ecc_sec_pipe0_count);
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nvgpu_kfree(g, ecc->gr.tex_unique_ecc_ded_pipe0_count);
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nvgpu_kfree(g, ecc->gr.tex_ecc_total_sec_pipe1_count);
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nvgpu_kfree(g, ecc->gr.tex_ecc_total_ded_pipe1_count);
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nvgpu_kfree(g, ecc->gr.tex_unique_ecc_sec_pipe1_count);
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nvgpu_kfree(g, ecc->gr.tex_unique_ecc_ded_pipe1_count);
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nvgpu_kfree(g, ecc->gr.sm_l1_tag_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.sm_l1_tag_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.sm_cbu_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.sm_cbu_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.sm_l1_data_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.sm_l1_data_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.sm_icache_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.sm_icache_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.gcc_l15_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.gcc_l15_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.gpccs_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.gpccs_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.mmu_l1tlb_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.mmu_l1tlb_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.fecs_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.fecs_ecc_uncorrected_err_count);
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for (i = 0; i < g->ltc_count; i++) {
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if (ecc->ltc.ecc_sec_count != NULL) {
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nvgpu_kfree(g, ecc->ltc.ecc_sec_count[i]);
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}
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if (ecc->ltc.ecc_ded_count != NULL) {
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nvgpu_kfree(g, ecc->ltc.ecc_ded_count[i]);
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}
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}
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nvgpu_kfree(g, ecc->ltc.ecc_sec_count);
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nvgpu_kfree(g, ecc->ltc.ecc_ded_count);
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nvgpu_kfree(g, ecc->fb.mmu_l2tlb_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->fb.mmu_l2tlb_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->fb.mmu_hubtlb_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->fb.mmu_hubtlb_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->fb.mmu_fillunit_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->fb.mmu_fillunit_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->pmu.pmu_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->pmu.pmu_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->fbpa.fbpa_ecc_sec_err_count);
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nvgpu_kfree(g, ecc->fbpa.fbpa_ecc_ded_err_count);
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(void)memset(ecc, 0, sizeof(*ecc));
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}
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int nvgpu_ecc_init_support(struct gk20a *g)
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{
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int err;
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if (g->ops.gr.init_ecc == NULL) {
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return 0;
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}
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nvgpu_ecc_init(g);
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err = g->ops.gr.init_ecc(g);
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if (err != 0) {
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return err;
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}
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err = nvgpu_ecc_sysfs_init(g);
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if (err != 0) {
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nvgpu_ecc_free(g);
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return err;
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}
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return 0;
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}
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void nvgpu_ecc_remove_support(struct gk20a *g)
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{
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if (g->ops.gr.init_ecc == NULL) {
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return;
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}
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nvgpu_ecc_sysfs_remove(g);
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nvgpu_ecc_free(g);
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}
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