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aa893ff77a
Linux specific code should have GPL license. Bug 2755169 Change-Id: I8cbf96f4be2e77fde01ef976a79ec6c578185c23 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2237105 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
148 lines
3.6 KiB
C
148 lines
3.6 KiB
C
/*
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* GP10B CDE
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*
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* Copyright (c) 2015-2019, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/gk20a.h>
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#include "cde_gp10b.h"
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enum gp10b_programs {
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GP10B_PROG_HPASS = 0,
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GP10B_PROG_HPASS_4K = 1,
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GP10B_PROG_VPASS = 2,
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GP10B_PROG_VPASS_4K = 3,
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GP10B_PROG_HPASS_DEBUG = 4,
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GP10B_PROG_HPASS_4K_DEBUG = 5,
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GP10B_PROG_VPASS_DEBUG = 6,
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GP10B_PROG_VPASS_4K_DEBUG = 7,
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GP10B_PROG_PASSTHROUGH = 8,
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};
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void gp10b_cde_get_program_numbers(struct gk20a *g,
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u32 block_height_log2,
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u32 shader_parameter,
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int *hprog_out, int *vprog_out)
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{
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int hprog, vprog;
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if (shader_parameter == 1) {
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hprog = GP10B_PROG_PASSTHROUGH;
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vprog = GP10B_PROG_PASSTHROUGH;
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} else {
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hprog = GP10B_PROG_HPASS;
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vprog = GP10B_PROG_VPASS;
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if (shader_parameter == 2) {
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hprog = GP10B_PROG_HPASS_DEBUG;
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vprog = GP10B_PROG_VPASS_DEBUG;
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}
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if (!nvgpu_iommuable(g)) {
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if (!g->mm.disable_bigpage) {
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nvgpu_warn(g,
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"When no IOMMU big pages cannot be used");
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}
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hprog |= 1;
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vprog |= 1;
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}
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}
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*hprog_out = hprog;
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*vprog_out = vprog;
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}
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bool gp10b_need_scatter_buffer(struct gk20a *g)
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{
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return !nvgpu_iommuable(g);
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}
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static u8 parity(u32 a)
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{
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a ^= a>>16u;
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a ^= a>>8u;
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a ^= a>>4u;
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a &= 0xfu;
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return (0x6996u >> a) & 1u;
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}
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int gp10b_populate_scatter_buffer(struct gk20a *g,
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struct sg_table *sgt,
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size_t surface_size,
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void *scatter_buffer_ptr,
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size_t scatter_buffer_size)
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{
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/* map scatter buffer to CPU VA and fill it */
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const u32 page_size_log2 = 12;
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const u32 page_size = 1 << page_size_log2;
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const u32 page_size_shift = page_size_log2 - 7u;
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/* 0011 1111 1111 1111 1111 1110 0100 1000 */
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const u32 getSliceMaskGP10B = 0x3ffffe48;
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u8 *scatter_buffer = scatter_buffer_ptr;
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size_t i;
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struct scatterlist *sg = NULL;
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u8 d = 0;
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size_t page = 0;
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size_t pages_left;
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surface_size = round_up(surface_size, page_size);
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pages_left = surface_size >> page_size_log2;
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if ((pages_left >> 3) > scatter_buffer_size)
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return -ENOMEM;
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for_each_sg(sgt->sgl, sg, sgt->nents, i) {
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unsigned int j;
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u64 surf_pa = sg_phys(sg);
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unsigned int n = (int)(sg->length >> page_size_log2);
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nvgpu_log(g, gpu_dbg_cde, "surfPA=0x%llx + %d pages", surf_pa, n);
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for (j=0; j < n && pages_left > 0; j++, surf_pa += page_size) {
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u32 addr = (((u32)(surf_pa>>7)) & getSliceMaskGP10B) >> page_size_shift;
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u8 scatter_bit = parity(addr);
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u8 bit = page & 7;
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d |= scatter_bit << bit;
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if (bit == 7) {
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scatter_buffer[page >> 3] = d;
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d = 0;
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}
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++page;
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--pages_left;
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}
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if (pages_left == 0)
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break;
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}
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/* write the last byte in case the number of pages is not divisible by 8 */
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if ((page & 7) != 0)
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scatter_buffer[page >> 3] = d;
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if (nvgpu_log_mask_enabled(g, gpu_dbg_cde)) {
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nvgpu_log(g, gpu_dbg_cde, "scatterBuffer content:");
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for (i = 0; i < page >> 3; i++) {
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nvgpu_log(g, gpu_dbg_cde, " %x", scatter_buffer[i]);
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}
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}
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return 0;
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}
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