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10be3e8778
Currently ACR header files are part of "include/nvgpu/acr/" folder & ACR interfaces are not used by any other UNIT which allows headers to keep restricted to ACR unit, as ACR can be divided into two stage process like blob preparation & bootstrap, so moved header files from of "include/nvgpu/acr/" to "nvgpu/common/acr/" to respective blob/ bootstrap/acr header files along with its dependent interfaces, this allows interfaces restricted to header file based on operation it does. With this any access to ACR must go through provided public functions, this header move change caused large code modification & required to make it with big single CL to avoid build break. JIRA NVGPU-2907 Change-Id: Idb24b17a35f7c7a85efe923c4e26edfd42b028e3 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2071393 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
141 lines
4.1 KiB
C
141 lines
4.1 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/firmware.h>
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#include <nvgpu/sec2if/sec2_if_cmn.h>
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#include "acr_blob_construct_v1.h"
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#include "acr_priv.h"
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#include "acr_gv100.h"
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#include "acr_tu104.h"
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#include "gv100/gsp_gv100.h"
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#include "tu104/sec2_tu104.h"
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static int tu104_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
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struct hs_acr *acr_type)
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{
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int err = 0;
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nvgpu_log_fn(g, " ");
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err = nvgpu_acr_bootstrap_hs_ucode(g, g->acr, &g->acr->acr_ahesasc);
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if (err != 0) {
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nvgpu_err(g, "ACR AHESASC bootstrap failed");
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goto exit;
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}
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err = nvgpu_acr_bootstrap_hs_ucode(g, g->acr, &g->acr->acr_asb);
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if (err != 0) {
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nvgpu_err(g, "ACR ASB bootstrap failed");
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goto exit;
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}
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exit:
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return err;
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}
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/* LSF init */
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static u32 tu104_acr_lsf_sec2(struct gk20a *g,
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struct acr_lsf_config *lsf)
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{
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/* SEC2 LS falcon info */
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lsf->falcon_id = FALCON_ID_SEC2;
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lsf->falcon_dma_idx = NV_SEC2_DMAIDX_UCODE;
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lsf->is_lazy_bootstrap = false;
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lsf->is_priv_load = false;
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lsf->get_lsf_ucode_details = nvgpu_acr_lsf_sec2_ucode_details_v1;
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lsf->get_cmd_line_args_offset = NULL;
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return BIT32(lsf->falcon_id);
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}
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/* ACR-AHESASC(ACR hub encryption setter and signature checker) init*/
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static void nvgpu_tu104_acr_ahesasc_sw_init(struct gk20a *g,
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struct hs_acr *acr_ahesasc)
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{
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struct hs_flcn_bl *hs_bl = &acr_ahesasc->acr_hs_bl;
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hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
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acr_ahesasc->acr_type = ACR_AHESASC;
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_PROD_UCODE;
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} else {
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acr_ahesasc->acr_fw_name = HSBIN_ACR_AHESASC_DBG_UCODE;
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}
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acr_ahesasc->ptr_bl_dmem_desc = &acr_ahesasc->bl_dmem_desc_v1;
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acr_ahesasc->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
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acr_ahesasc->acr_flcn = &g->sec2.flcn;
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acr_ahesasc->acr_flcn_setup_hw_and_bl_bootstrap =
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tu104_sec2_setup_hw_and_bl_bootstrap;
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}
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/* ACR-ASB(ACR SEC2 booter) init*/
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static void nvgpu_tu104_acr_asb_sw_init(struct gk20a *g,
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struct hs_acr *acr_asb)
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{
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struct hs_flcn_bl *hs_bl = &acr_asb->acr_hs_bl;
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hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE;
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acr_asb->acr_type = ACR_ASB;
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if (!g->ops.pmu.is_debug_mode_enabled(g)) {
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acr_asb->acr_fw_name = HSBIN_ACR_ASB_PROD_UCODE;
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} else {
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acr_asb->acr_fw_name = HSBIN_ACR_ASB_DBG_UCODE;
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}
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acr_asb->ptr_bl_dmem_desc = &acr_asb->bl_dmem_desc_v1;
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acr_asb->bl_dmem_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
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acr_asb->acr_flcn = &g->gsp_flcn;
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acr_asb->acr_flcn_setup_hw_and_bl_bootstrap =
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gv100_gsp_setup_hw_and_bl_bootstrap;
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}
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void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
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{
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nvgpu_log_fn(g, " ");
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/* Inherit settings from older chip */
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nvgpu_gv100_acr_sw_init(g, acr);
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acr->lsf_enable_mask |= tu104_acr_lsf_sec2(g,
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&acr->lsf[FALCON_ID_SEC2]);
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acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob_v1;
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acr->bootstrap_owner = FALCON_ID_GSPLITE;
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acr->bootstrap_hs_acr = tu104_bootstrap_hs_acr;
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/* Init ACR-AHESASC */
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nvgpu_tu104_acr_ahesasc_sw_init(g, &acr->acr_ahesasc);
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/* Init ACR-ASB*/
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nvgpu_tu104_acr_asb_sw_init(g, &acr->acr_asb);
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}
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