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d717c69d2b
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the css sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3bf696e13d359982c964c7bc470500a30555c034 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514205 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
137 lines
3.9 KiB
C
137 lines
3.9 KiB
C
/*
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* GK20A Cycle stats snapshots support (subsystem for gr_gk20a).
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*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CSS_GR_GK20A_H
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#define CSS_GR_GK20A_H
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/* the minimal size of HW buffer - should be enough to avoid HW overflows */
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#define CSS_MIN_HW_SNAPSHOT_SIZE (8 * 1024 * 1024)
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/* cycle stats fifo header (must match NvSnapshotBufferFifo) */
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struct gk20a_cs_snapshot_fifo {
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/* layout description of the buffer */
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u32 start;
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u32 end;
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/* snafu bits */
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u32 hw_overflow_events_occured;
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u32 sw_overflow_events_occured;
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/* the kernel copies new entries to put and
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* increment the put++. if put == get then
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* overflowEventsOccured++
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*/
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u32 put;
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u32 _reserved10;
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u32 _reserved11;
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u32 _reserved12;
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/* the driver/client reads from get until
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* put==get, get++ */
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u32 get;
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u32 _reserved20;
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u32 _reserved21;
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u32 _reserved22;
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/* unused */
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u32 _reserved30;
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u32 _reserved31;
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u32 _reserved32;
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u32 _reserved33;
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};
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/* cycle stats fifo entry (must match NvSnapshotBufferFifoEntry) */
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struct gk20a_cs_snapshot_fifo_entry {
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/* global 48 timestamp */
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u32 timestamp31_00:32;
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u32 timestamp39_32:8;
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/* id of perfmon, should correlate with CSS_MAX_PERFMON_IDS */
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u32 perfmon_id:8;
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/* typically samples_counter is wired to #pmtrigger count */
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u32 samples_counter:12;
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/* DS=Delay Sample, SZ=Size (0=32B, 1=16B) */
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u32 ds:1;
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u32 sz:1;
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u32 zero0:1;
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u32 zero1:1;
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/* counter results */
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u32 event_cnt:32;
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u32 trigger0_cnt:32;
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u32 trigger1_cnt:32;
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u32 sample_cnt:32;
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/* Local PmTrigger results for Maxwell+ or padding otherwise */
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u16 local_trigger_b_count:16;
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u16 book_mark_b:16;
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u16 local_trigger_a_count:16;
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u16 book_mark_a:16;
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};
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/* cycle stats snapshot client data (e.g. associated with channel) */
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struct gk20a_cs_snapshot_client {
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struct nvgpu_list_node list;
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u32 dmabuf_fd;
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struct dma_buf *dma_handler;
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struct gk20a_cs_snapshot_fifo *snapshot;
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u32 snapshot_size;
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u32 perfmon_start;
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u32 perfmon_count;
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};
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static inline struct gk20a_cs_snapshot_client *
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gk20a_cs_snapshot_client_from_list(struct nvgpu_list_node *node)
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{
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return (struct gk20a_cs_snapshot_client *)
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((uintptr_t)node - offsetof(struct gk20a_cs_snapshot_client, list));
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};
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/* should correlate with size of gk20a_cs_snapshot_fifo_entry::perfmon_id */
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#define CSS_MAX_PERFMON_IDS 256
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/* local definitions to avoid hardcodes sizes and shifts */
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#define PM_BITMAP_SIZE DIV_ROUND_UP(CSS_MAX_PERFMON_IDS, BITS_PER_LONG)
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/* cycle stats snapshot control structure for one HW entry and many clients */
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struct gk20a_cs_snapshot {
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unsigned long perfmon_ids[PM_BITMAP_SIZE];
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struct nvgpu_list_node clients;
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struct nvgpu_mem hw_memdesc;
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/* pointer to allocated cpu_va memory where GPU place data */
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struct gk20a_cs_snapshot_fifo_entry *hw_snapshot;
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struct gk20a_cs_snapshot_fifo_entry *hw_end;
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struct gk20a_cs_snapshot_fifo_entry *hw_get;
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};
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inline void css_hw_set_handled_snapshots(struct gk20a *g, u32 done);
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int css_hw_enable_snapshot(struct channel_gk20a *ch,
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struct gk20a_cs_snapshot_client *cs_client);
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void css_hw_disable_snapshot(struct gr_gk20a *gr);
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u32 css_gr_allocate_perfmon_ids(struct gk20a_cs_snapshot *data,
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u32 count);
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u32 css_gr_release_perfmon_ids(struct gk20a_cs_snapshot *data,
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u32 start,
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u32 count);
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int css_hw_check_data_available(struct channel_gk20a *ch, u32 *pending,
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bool *hw_overflow);
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#endif /* CSS_GR_GK20A_H */
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