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1146dbae18
Add support for gp10b freq scaling. Bug 200147662 Reviewed-on: http://git-master/r/816962 (cherry picked from commit 62de7dba758e46ee80c896dcfcbccb0f8b979438) Change-Id: I71ddfa394d490c002761d2a8bbb95090a4c0e799 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/834758 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
348 lines
8.8 KiB
C
348 lines
8.8 KiB
C
/*
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* drivers/video/tegra/host/gk20a/platform_gk20a_tegra.c
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*
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* GK20A Tegra Platform Interface
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*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/of_platform.h>
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#include <linux/nvhost.h>
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#include <linux/debugfs.h>
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#include <linux/tegra-powergate.h>
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#include <linux/platform_data/tegra_edp.h>
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#include <uapi/linux/nvgpu.h>
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#include <linux/dma-buf.h>
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#include <linux/nvmap.h>
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#include <linux/tegra_pm_domains.h>
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#include <linux/reset.h>
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#include <soc/tegra/tegra_bpmp.h>
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#include "gk20a/platform_gk20a.h"
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#include "gk20a/gk20a.h"
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#include "platform_tegra.h"
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#define GP10B_MAX_SUPPORTED_FREQS 11
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unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS];
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static struct {
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char *name;
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unsigned long default_rate;
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} tegra_gp10b_clocks[] = {
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{"gpu", 1000000000},
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{"gpu_sys", 204000000} };
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/*
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* gp10b_tegra_get_clocks()
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*
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* This function finds clocks in tegra platform and populates
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* the clock information to gp10b platform data.
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*/
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static int gp10b_tegra_get_clocks(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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struct gk20a *g = get_gk20a(pdev);
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struct device *dev = dev_from_gk20a(g);
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int i;
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if (tegra_platform_is_linsim())
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return 0;
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platform->num_clks = 0;
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for (i = 0; i < ARRAY_SIZE(tegra_gp10b_clocks); i++) {
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long rate = tegra_gp10b_clocks[i].default_rate;
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struct clk *c;
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c = clk_get(dev, tegra_gp10b_clocks[i].name);
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if (IS_ERR(c)) {
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gk20a_err(&pdev->dev, "cannot get clock %s",
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tegra_gp10b_clocks[i].name);
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} else {
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clk_set_rate(c, rate);
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platform->clk[i] = c;
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}
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}
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platform->num_clks = i;
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return 0;
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}
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static int gp10b_tegra_probe(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(pdev);
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struct device_node *np = pdev->dev.of_node;
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struct device_node *host1x_node;
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struct platform_device *host1x_pdev;
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const __be32 *host1x_ptr;
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host1x_ptr = of_get_property(np, "nvidia,host1x", NULL);
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if (!host1x_ptr) {
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gk20a_err(&pdev->dev, "host1x device not available");
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return -ENOSYS;
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}
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host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr));
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host1x_pdev = of_find_device_by_node(host1x_node);
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if (!host1x_pdev) {
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gk20a_err(&pdev->dev, "host1x device not available");
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return -ENOSYS;
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}
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platform->g->host1x_dev = host1x_pdev;
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platform->bypass_smmu = !device_is_iommuable(&pdev->dev);
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platform->disable_bigpage = platform->bypass_smmu;
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platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
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= false;
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platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
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= false;
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platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false;
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platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false;
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platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_gfxp =
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debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR,
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platform->debugfs,
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&platform->g->gr.t18x.ctx_vars.force_preemption_gfxp);
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platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_cilp =
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debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR,
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platform->debugfs,
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&platform->g->gr.t18x.ctx_vars.force_preemption_cilp);
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platform->g->gr.t18x.ctx_vars.debugfs_dump_ctxsw_stats =
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debugfs_create_bool("dump_ctxsw_stats_on_channel_close",
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S_IRUGO|S_IWUSR,
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platform->debugfs,
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&platform->g->gr.t18x.
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ctx_vars.dump_ctxsw_stats_on_channel_close);
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gp10b_tegra_get_clocks(pdev);
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return 0;
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}
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static int gp10b_tegra_late_probe(struct platform_device *pdev)
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{
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/* Make gk20a power domain a subdomain of host1x */
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nvhost_register_client_domain(dev_to_genpd(&pdev->dev));
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return 0;
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}
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static int gp10b_tegra_remove(struct platform_device *pdev)
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{
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/* remove gk20a power subdomain from host1x */
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nvhost_unregister_client_domain(dev_to_genpd(&pdev->dev));
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return 0;
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}
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static bool gp10b_tegra_is_railgated(struct platform_device *pdev)
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{
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bool ret = false;
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if (tegra_bpmp_running())
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ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU);
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return ret;
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}
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static int gp10b_tegra_railgate(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(pdev);
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if (tegra_bpmp_running() &&
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tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) {
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int i;
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for (i = 0; i < platform->num_clks; i++) {
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if (platform->clk[i])
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clk_disable_unprepare(platform->clk[i]);
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}
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tegra_powergate_partition(TEGRA_POWERGATE_GPU);
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}
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return 0;
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}
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static int gp10b_tegra_unrailgate(struct platform_device *pdev)
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{
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int ret = 0;
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struct gk20a_platform *platform = gk20a_get_platform(pdev);
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if (tegra_bpmp_running()) {
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int i;
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ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU);
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for (i = 0; i < platform->num_clks; i++) {
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if (platform->clk[i])
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clk_prepare_enable(platform->clk[i]);
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}
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}
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return ret;
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}
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static int gp10b_tegra_suspend(struct device *dev)
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{
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return 0;
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}
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static int gp10b_tegra_reset_assert(struct platform_device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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int ret = 0;
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if (!platform->reset_control)
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return -EINVAL;
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ret = reset_control_assert(platform->reset_control);
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return ret;
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}
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static int gp10b_tegra_reset_deassert(struct platform_device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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int ret = 0;
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if (!platform->reset_control)
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return -EINVAL;
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ret = reset_control_deassert(platform->reset_control);
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return ret;
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}
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static void gp10b_tegra_prescale(struct platform_device *pdev)
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{
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struct gk20a *g = get_gk20a(pdev);
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u32 avg = 0;
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gk20a_dbg_fn("");
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gk20a_pmu_load_norm(g, &avg);
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/* TBD - Notify EDP about changed constrains */
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gk20a_dbg_fn("done");
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}
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static void gp10b_tegra_postscale(struct platform_device *pdev,
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unsigned long freq)
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{
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/* TBD - notify EMC about frequency change */
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gk20a_dbg_fn("");
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}
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static unsigned long gp10b_get_clk_rate(struct platform_device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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return clk_get_rate(platform->clk[0]);
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}
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static long gp10b_round_clk_rate(struct platform_device *dev,
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unsigned long rate)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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return clk_round_rate(platform->clk[0], rate);
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}
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static int gp10b_set_clk_rate(struct platform_device *dev, unsigned long rate)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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return clk_set_rate(platform->clk[0], rate);
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}
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static int gp10b_clk_get_freqs(struct platform_device *pdev,
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unsigned long **freqs, int *num_freqs)
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{
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struct gk20a_platform *platform = gk20a_get_platform(pdev);
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unsigned long min_rate, max_rate, freq_step, rate;
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int i;
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min_rate = clk_round_rate(platform->clk[0], 0);
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max_rate = clk_round_rate(platform->clk[0], (UINT_MAX - 1));
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freq_step = (max_rate - min_rate)/(GP10B_MAX_SUPPORTED_FREQS - 1);
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gk20a_dbg_info("min rate: %ld max rate: %ld freq step %ld\n",
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min_rate, max_rate, freq_step);
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for (i = 0; i < GP10B_MAX_SUPPORTED_FREQS; i++) {
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rate = min_rate + i * freq_step;
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gp10b_freq_table[i] = clk_round_rate(platform->clk[0], rate);
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}
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/* Fill freq table */
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*freqs = gp10b_freq_table;
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*num_freqs = GP10B_MAX_SUPPORTED_FREQS;
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return 0;
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}
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struct gk20a_platform t18x_gpu_tegra_platform = {
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.has_syncpoints = true,
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/* power management configuration */
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.railgate_delay = 500,
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.clockgate_delay = 50,
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/* power management configuration */
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.can_railgate = false,
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.enable_elpg = false,
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.enable_blcg = true,
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.enable_slcg = true,
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.enable_elcg = true,
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/* ptimer src frequency in hz*/
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.ptimer_src_freq = 31250000,
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.ch_wdt_timeout_ms = 5000,
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.probe = gp10b_tegra_probe,
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.late_probe = gp10b_tegra_late_probe,
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.remove = gp10b_tegra_remove,
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/* power management callbacks */
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.suspend = gp10b_tegra_suspend,
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.railgate = gp10b_tegra_railgate,
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.unrailgate = gp10b_tegra_unrailgate,
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.is_railgated = gp10b_tegra_is_railgated,
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.busy = gk20a_tegra_busy,
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.idle = gk20a_tegra_idle,
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.dump_platform_dependencies = gk20a_tegra_debug_dump,
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.default_big_page_size = SZ_64K,
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.has_cde = true,
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.clk_get_rate = gp10b_get_clk_rate,
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.clk_round_rate = gp10b_round_clk_rate,
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.clk_set_rate = gp10b_set_clk_rate,
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.get_clk_freqs = gp10b_clk_get_freqs,
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/* frequency scaling configuration */
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.prescale = gp10b_tegra_prescale,
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.postscale = gp10b_tegra_postscale,
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.devfreq_governor = "nvhost_podgov",
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.qos_id = PM_QOS_GPU_FREQ_MIN,
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.secure_alloc = gk20a_tegra_secure_alloc,
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.secure_page_alloc = gk20a_tegra_secure_page_alloc,
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.reset_assert = gp10b_tegra_reset_assert,
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.reset_deassert = gp10b_tegra_reset_deassert,
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.force_reset_in_do_idle = true,
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};
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