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Change a check from CONFIG_NVGPU_NON_FUSA to CONFIG_NVGPU_DGPU as the gpccount is more than 1 for DGPU and this code need to be executed for DGPU. Jira NVGPU-4460 Change-Id: I806c926cd787c787ac8a04f998602edcae5419b8 Signed-off-by: vinodg <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2257036 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
226 lines
7.1 KiB
C
226 lines
7.1 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gr/gr_ecc.h>
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#include <nvgpu/gr/gr_utils.h>
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#include <nvgpu/gr/config.h>
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#include <nvgpu/string.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/ecc.h>
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int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
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struct nvgpu_ecc_stat ***stat, const char *name)
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{
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struct nvgpu_ecc_stat **stats;
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struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
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u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr_config);
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u32 gpc, tpc;
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char gpc_str[10] = {0}, tpc_str[10] = {0};
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int err = 0;
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stats = nvgpu_kzalloc(g, nvgpu_safe_mult_u64(sizeof(*stats),
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gpc_count));
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if (stats == NULL) {
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return -ENOMEM;
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}
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for (gpc = 0; gpc < gpc_count; gpc++) {
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stats[gpc] = nvgpu_kzalloc(g,
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nvgpu_safe_mult_u64(sizeof(*stats[gpc]),
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nvgpu_gr_config_get_gpc_tpc_count(gr_config,
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gpc)));
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if (stats[gpc] == NULL) {
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err = -ENOMEM;
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goto fail;
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}
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}
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for (gpc = 0; gpc < gpc_count; gpc++) {
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for (tpc = 0;
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tpc < nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc);
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tpc++) {
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/**
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* Store stats name as below:
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* gpc<gpc_value>_tpc<tpc_value>_<name_string>
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*/
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(void)strcpy(stats[gpc][tpc].name, "gpc");
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(void)nvgpu_strnadd_u32(gpc_str, gpc,
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sizeof(gpc_str), 10U);
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(void)strncat(stats[gpc][tpc].name, gpc_str,
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NVGPU_ECC_STAT_NAME_MAX_SIZE -
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strlen(stats[gpc][tpc].name));
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(void)strncat(stats[gpc][tpc].name, "_tpc",
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NVGPU_ECC_STAT_NAME_MAX_SIZE -
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strlen(stats[gpc][tpc].name));
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(void)nvgpu_strnadd_u32(tpc_str, tpc,
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sizeof(tpc_str), 10U);
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(void)strncat(stats[gpc][tpc].name, tpc_str,
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NVGPU_ECC_STAT_NAME_MAX_SIZE -
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strlen(stats[gpc][tpc].name));
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(void)strncat(stats[gpc][tpc].name, "_",
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NVGPU_ECC_STAT_NAME_MAX_SIZE -
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strlen(stats[gpc][tpc].name));
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(void)strncat(stats[gpc][tpc].name, name,
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NVGPU_ECC_STAT_NAME_MAX_SIZE -
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strlen(stats[gpc][tpc].name));
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nvgpu_ecc_stat_add(g, &stats[gpc][tpc]);
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}
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}
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*stat = stats;
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fail:
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if (err != 0) {
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#ifdef CONFIG_NVGPU_DGPU
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while (gpc-- != 0u) {
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nvgpu_kfree(g, stats[gpc]);
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}
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#endif
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nvgpu_kfree(g, stats);
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}
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return err;
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}
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int nvgpu_ecc_counter_init_per_gpc(struct gk20a *g,
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struct nvgpu_ecc_stat **stat, const char *name)
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{
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struct nvgpu_ecc_stat *stats;
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struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
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u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr_config);
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u32 gpc;
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char gpc_str[10] = {0};
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stats = nvgpu_kzalloc(g, nvgpu_safe_mult_u64(sizeof(*stats),
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gpc_count));
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if (stats == NULL) {
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return -ENOMEM;
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}
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for (gpc = 0; gpc < gpc_count; gpc++) {
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/**
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* Store stats name as below:
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* gpc<gpc_value>_<name_string>
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*/
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(void)strcpy(stats[gpc].name, "gpc");
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(void)nvgpu_strnadd_u32(gpc_str, gpc, sizeof(gpc_str), 10U);
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(void)strncat(stats[gpc].name, gpc_str,
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NVGPU_ECC_STAT_NAME_MAX_SIZE -
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strlen(stats[gpc].name));
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(void)strncat(stats[gpc].name, "_",
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NVGPU_ECC_STAT_NAME_MAX_SIZE -
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strlen(stats[gpc].name));
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(void)strncat(stats[gpc].name, name,
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NVGPU_ECC_STAT_NAME_MAX_SIZE -
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strlen(stats[gpc].name));
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nvgpu_ecc_stat_add(g, &stats[gpc]);
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}
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*stat = stats;
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return 0;
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}
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/* helper function that frees the count array if non-NULL. */
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static void free_ecc_stat_count_array(struct gk20a *g,
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struct nvgpu_ecc_stat **stat,
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u32 gpc_count)
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{
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u32 i;
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if (stat != NULL) {
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for (i = 0; i < gpc_count; i++) {
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nvgpu_kfree(g, stat[i]);
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}
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nvgpu_kfree(g, stat);
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}
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}
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void nvgpu_gr_ecc_free(struct gk20a *g)
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{
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struct nvgpu_ecc *ecc = &g->ecc;
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struct nvgpu_gr_config *gr_config = nvgpu_gr_get_config_ptr(g);
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u32 gpc_count;
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if (gr_config == NULL) {
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return;
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}
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gpc_count = nvgpu_gr_config_get_gpc_count(gr_config);
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free_ecc_stat_count_array(g, ecc->gr.sm_lrf_ecc_single_err_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.sm_lrf_ecc_double_err_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.sm_shm_ecc_sec_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.sm_shm_ecc_sed_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.sm_shm_ecc_ded_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.tex_ecc_total_sec_pipe0_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.tex_ecc_total_ded_pipe0_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.tex_unique_ecc_sec_pipe0_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.tex_unique_ecc_ded_pipe0_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.tex_ecc_total_sec_pipe1_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.tex_ecc_total_ded_pipe1_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.tex_unique_ecc_sec_pipe1_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.tex_unique_ecc_ded_pipe1_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.sm_l1_tag_ecc_corrected_err_count,
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gpc_count);
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free_ecc_stat_count_array(g,
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ecc->gr.sm_l1_tag_ecc_uncorrected_err_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.sm_cbu_ecc_corrected_err_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.sm_cbu_ecc_uncorrected_err_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.sm_l1_data_ecc_corrected_err_count,
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gpc_count);
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free_ecc_stat_count_array(g,
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ecc->gr.sm_l1_data_ecc_uncorrected_err_count,
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gpc_count);
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free_ecc_stat_count_array(g, ecc->gr.sm_icache_ecc_corrected_err_count,
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gpc_count);
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free_ecc_stat_count_array(g,
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ecc->gr.sm_icache_ecc_uncorrected_err_count,
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gpc_count);
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nvgpu_kfree(g, ecc->gr.gcc_l15_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.gcc_l15_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.gpccs_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.gpccs_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.mmu_l1tlb_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.mmu_l1tlb_ecc_uncorrected_err_count);
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nvgpu_kfree(g, ecc->gr.fecs_ecc_corrected_err_count);
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nvgpu_kfree(g, ecc->gr.fecs_ecc_uncorrected_err_count);
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}
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