mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
2df0b39957
fb_surface payload used to send boardobjs for GV100 dGPU, but these are not required as Turing uses super surface to share boardobjs with PMU Microcode. JIRA NVGPU-4446 Change-Id: I295a0768bbed6e2dc385c33113669b0ca0a1b9b4 Signed-off-by: mkumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2265594 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
90 lines
2.8 KiB
C
90 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu/allocator.h>
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#include <nvgpu/allocator.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/pmu.h>
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#include <nvgpu/pmu/fw.h>
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#include <nvgpu/dma.h>
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void nvgpu_pmu_dmem_allocator_init(struct gk20a *g,
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struct nvgpu_pmu *pmu, struct nvgpu_allocator *dmem,
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union pmu_init_msg_pmu *init)
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{
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struct pmu_fw_ver_ops *fw_ops = &pmu->fw->ops;
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if (!nvgpu_alloc_initialized(dmem)) {
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/* Align start and end addresses */
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u32 start =
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ALIGN(U32(fw_ops->get_init_msg_sw_mngd_area_off(init)),
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PMU_DMEM_ALLOC_ALIGNMENT);
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u32 end = (U32(fw_ops->get_init_msg_sw_mngd_area_off(init)) +
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U32(fw_ops->get_init_msg_sw_mngd_area_size(init))) &
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~(PMU_DMEM_ALLOC_ALIGNMENT - 1U);
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u32 size = end - start;
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nvgpu_allocator_init(g, dmem, NULL, "gk20a_pmu_dmem", start,
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size, PMU_DMEM_ALLOC_ALIGNMENT, 0ULL, 0ULL,
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BITMAP_ALLOCATOR);
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}
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}
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void nvgpu_pmu_dmem_allocator_destroy(struct nvgpu_allocator *dmem)
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{
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if (nvgpu_alloc_initialized(dmem)) {
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nvgpu_alloc_destroy(dmem);
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}
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}
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void nvgpu_pmu_surface_free(struct gk20a *g, struct nvgpu_mem *mem)
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{
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if (nvgpu_mem_is_valid(mem)) {
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nvgpu_dma_free(g, mem);
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}
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}
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void nvgpu_pmu_surface_describe(struct gk20a *g, struct nvgpu_mem *mem,
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struct flcn_mem_desc_v0 *fb)
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{
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fb->address.lo = u64_lo32(mem->gpu_va);
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fb->address.hi = u64_hi32(mem->gpu_va);
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fb->params = ((u32)mem->size & 0xFFFFFFU);
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fb->params |= (GK20A_PMU_DMAIDX_VIRT << 24U);
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}
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int nvgpu_pmu_sysmem_surface_alloc(struct gk20a *g, struct nvgpu_mem *mem,
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u32 size)
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{
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struct mm_gk20a *mm = &g->mm;
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struct vm_gk20a *vm = mm->pmu.vm;
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int err;
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err = nvgpu_dma_alloc_map_sys(vm, size, mem);
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if (err != 0) {
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nvgpu_err(g, "failed to allocate memory\n");
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return -ENOMEM;
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}
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return 0;
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}
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