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fba516ffae
PMU IRQs were not enabled assuming entire functionality for LS PMU. Debugging early init issues of PMU falcon ECC errors triggered during nvgpu power-on will be cumbersome if interrupts are not enabled early. FMEA analysis of the nvgpu init path also requires this interrupt be enabled earlier. Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron. pmu_enable_irq is updated to enable interrupts differently for safety and non-safety. PMU interrupts disabling is moved out of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new wrapper API nvgpu_pmu_enable_irq. PMU ECC init and isr mutex init is moved to the beginning of nvgpu_pmu_early_init as for safety, ls pmu code path is disabled. Fixed the pmu_early_init dependent and mc interrupt related unit tests. Update the doxygen for changed functions. JIRA NVGPU-4439 Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2251732 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
74 lines
2.9 KiB
C
74 lines
2.9 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef PMU_GV11B_H
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#define PMU_GV11B_H
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_hw_err_inject_info;
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struct nvgpu_hw_err_inject_info_desc;
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bool gv11b_pmu_is_debug_mode_en(struct gk20a *g);
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void gv11b_pmu_flcn_setup_boot_config(struct gk20a *g);
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void gv11b_setup_apertures(struct gk20a *g);
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void gv11b_write_dmatrfbase(struct gk20a *g, u32 addr);
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bool gv11b_pmu_is_engine_in_reset(struct gk20a *g);
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void gv11b_pmu_engine_reset(struct gk20a *g, bool do_reset);
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u32 gv11b_pmu_falcon_base_addr(void);
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void gv11b_secured_pmu_start(struct gk20a *g);
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bool gv11b_is_pmu_supported(struct gk20a *g);
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int gv11b_pmu_correct_ecc(struct gk20a *g, u32 ecc_status, u32 ecc_addr);
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void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0);
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#ifdef CONFIG_NVGPU_LS_PMU
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int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
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u32 args_offset);
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void gv11b_pmu_setup_elpg(struct gk20a *g);
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u32 gv11b_pmu_queue_head_r(u32 i);
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u32 gv11b_pmu_queue_head__size_1_v(void);
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u32 gv11b_pmu_queue_tail_r(u32 i);
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u32 gv11b_pmu_queue_tail__size_1_v(void);
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u32 gv11b_pmu_mutex__size_1_v(void);
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#endif
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void gv11b_clear_pmu_bar0_host_err_status(struct gk20a *g);
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int gv11b_pmu_bar0_error_status(struct gk20a *g, u32 *bar0_status,
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u32 *etype);
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bool gv11b_pmu_validate_mem_integrity(struct gk20a *g);
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#ifdef CONFIG_NVGPU_INJECT_HWERR
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struct nvgpu_hw_err_inject_info_desc * gv11b_pmu_intr_get_err_desc(struct gk20a *g);
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void gv11b_pmu_inject_ecc_error(struct gk20a *g,
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struct nvgpu_hw_err_inject_info *err, u32 error_info);
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#endif /* CONFIG_NVGPU_INJECT_HWERR */
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int gv11b_pmu_ecc_init(struct gk20a *g);
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void gv11b_pmu_ecc_free(struct gk20a *g);
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u32 gv11b_pmu_get_irqdest(struct gk20a *g);
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void gv11b_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable);
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#endif /* PMU_GV11B_H */
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