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252ddc4f05
Add macros for whitelisting coverity violations. These macros use pragma directives. The pragma directives and whitelisting macros are only enabled when a coverity scan is being run. The whitelisting macros have been added to a new header called static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have been moved into static_analysis.h because this will be the new header for static analysis related macros/defines/etc. JIRA NVGPU-3820 Change-Id: I9c63f20f670880b420415535738034619314b7c3 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2180600 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
/*
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* GV11B syncpt cmdbuf
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*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/mm.h>
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#include <nvgpu/vm.h>
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#include <nvgpu/gmmu.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/lock.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/nvhost.h>
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#include <nvgpu/static_analysis.h>
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#include "syncpt_cmdbuf_gv11b.h"
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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void gv11b_syncpt_add_wait_cmd(struct gk20a *g,
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struct priv_cmd_entry *cmd, u32 off,
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u32 id, u32 thresh, u64 gpu_va_base)
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{
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u64 gpu_va = gpu_va_base +
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nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(id);
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nvgpu_log_fn(g, " ");
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off = cmd->off + off;
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/* sema_addr_lo */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017);
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nvgpu_mem_wr32(g, cmd->mem, off++,
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nvgpu_safe_cast_u64_to_u32(gpu_va & 0xffffffffU));
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/* sema_addr_hi */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018);
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nvgpu_mem_wr32(g, cmd->mem, off++,
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nvgpu_safe_cast_u64_to_u32((gpu_va >> 32U) & 0xffU));
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/* payload_lo */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019);
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nvgpu_mem_wr32(g, cmd->mem, off++, thresh);
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/* payload_hi : ignored */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a);
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nvgpu_mem_wr32(g, cmd->mem, off++, 0U);
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/* sema_execute : acq_strict_geq | switch_en | 32bit */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
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nvgpu_mem_wr32(g, cmd->mem, off, 0x2U | ((u32)1U << 12U));
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}
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u32 gv11b_syncpt_get_wait_cmd_size(void)
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{
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return 10U;
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}
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u32 gv11b_syncpt_get_incr_per_release(void)
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{
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return 1U;
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}
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void gv11b_syncpt_add_incr_cmd(struct gk20a *g,
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bool wfi_cmd, struct priv_cmd_entry *cmd,
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u32 id, u64 gpu_va)
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{
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u32 off = cmd->off;
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nvgpu_log_fn(g, " ");
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/* sema_addr_lo */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017);
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nvgpu_mem_wr32(g, cmd->mem, off++,
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nvgpu_safe_cast_u64_to_u32(gpu_va & 0xffffffffU));
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/* sema_addr_hi */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018);
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nvgpu_mem_wr32(g, cmd->mem, off++,
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nvgpu_safe_cast_u64_to_u32((gpu_va >> 32U) & 0xffU));
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/* payload_lo */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019);
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nvgpu_mem_wr32(g, cmd->mem, off++, 0);
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/* payload_hi : ignored */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a);
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nvgpu_mem_wr32(g, cmd->mem, off++, 0);
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/* sema_execute : release | wfi | 32bit */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
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nvgpu_mem_wr32(g, cmd->mem, off, (0x1U |
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((u32)(wfi_cmd ? 0x1U : 0x0U) << 20U)));
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}
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u32 gv11b_syncpt_get_incr_cmd_size(bool wfi_cmd)
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{
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return 10U;
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}
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#endif
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