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a295d90cac
Extend the existing NVGPU_GPU_IOCTL_OPEN_CHANNEL interface to allow opening channels for other than the primary (i.e., the graphics) runlists. This is required to push work to dGPU engines that have their own runlists, such as the asynchronous copy engines and the multimedia engines. Minor change - Added active_engines_list allocation and assignment for fifo_vgpu back end. JIRA DNVGPU-25 Change-Id: I3ed377e2c9a2b4dd72e8256463510a62c64e7a8f Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1161541 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
/*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TSG_GK20A_H_
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#define __TSG_GK20A_H_
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#define NVGPU_INVALID_TSG_ID (-1)
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bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch);
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int gk20a_tsg_dev_release(struct inode *inode, struct file *filp);
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int gk20a_tsg_dev_open(struct inode *inode, struct file *filp);
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int gk20a_tsg_open(struct gk20a *g, struct file *filp);
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long gk20a_tsg_dev_ioctl(struct file *filp,
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unsigned int cmd, unsigned long arg);
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int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid);
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void gk20a_init_tsg_ops(struct gpu_ops *gops);
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struct tsg_gk20a {
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struct gk20a *g;
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bool in_use;
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int tsgid;
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struct kref refcount;
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struct list_head ch_list;
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int num_active_channels;
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struct mutex ch_list_lock;
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int timeslice_us;
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int timeslice_timeout;
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int timeslice_scale;
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struct gr_ctx_desc *tsg_gr_ctx;
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struct vm_gk20a *vm;
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u32 interleave_level;
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struct list_head event_id_list;
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struct mutex event_id_list_lock;
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u32 runlist_id;
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};
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int gk20a_enable_tsg(struct tsg_gk20a *tsg);
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int gk20a_disable_tsg(struct tsg_gk20a *tsg);
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int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg,
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struct channel_gk20a *ch);
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int gk20a_tsg_unbind_channel(struct channel_gk20a *ch);
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void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
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int event_id);
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#endif /* __TSG_GK20A_H_ */
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