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132f9bdab2
hw register checker detects and error on local setup by nvdvms team. register readout in GVS and nvdvms team setup is different. On Finial System, Checker is expected to run after init But on GVS, Checker runs as a test case along with test other GPU tests. This lead to mismatch between local and gvs testing. register missmatch detected by an hw register checker is not really an error, its related to information. There are two cases for updating mask value 1. These interrupts are mainly for sw information not any errors 2. These are temporary values ready from board We will update these values again once we get finial list from HW team so, we can avoid checking bits 4:7, which represents * NV_RUNLIST_INTR_0_RUNLIST_IDLE 4U:4U /* RWIVF */ * NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE 5U:5U /* RWXVF */ * NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE 6U:6U /* RWXVF */ * NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE 7U:7U /* RWXVF */ Bug 3912656 Change-Id: I75d1d4737897ef44e78329ed708e86637e8bcf48 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2831273 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-by: Ankur Kishore <ankkishore@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>