Sai Nikhil e824ea0963 gpu: nvgpu: common: MISRA Rule 10.1 fixes ...

MISRA rule 10.1 mandates that the correct data types are used as
operands of operators. For example, only unsigned integers can be used
as operands of bitwise operators.

This patch fixes rule 10.1 vioaltions for drivers/gpu/nvgpu/common.

JIRA NVGPU-777
JIRA NVGPU-1006

Change-Id: I53fe750f1b41816a183c595e5beb7bd263c27725
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971221
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-01-06 19:24:58 -08:00

..

sec2_ipc.c

gpu: nvgpu: make flcn queues struct nvgpu_falcon_queue*

2019-01-03 02:58:42 -08:00

sec2.c

gpu: nvgpu: common: MISRA Rule 10.1 fixes

2019-01-06 19:24:58 -08:00