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4e85ebc05f
A naked channel ID does not carry good information about the channel validity and is a very low level construct for an API of this level. Refactor the runlist updating fifo APIs to take a channel pointer. While at it, delete the channel and wait_for_finish parameters from gk20a_fifo_update_runlist_ids() - the only caller is suspend and resume and the parameters were always null for channel and true for wait. Jira NVGPU-1309 Jira NVGPU-1737 Change-Id: Ied350bc8e482d8e311cc708ab0c7afdf315c61cc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1997744 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
67 lines
2.9 KiB
C
67 lines
2.9 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _FIFO_VGPU_H_
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#define _FIFO_VGPU_H_
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#include <nvgpu/types.h>
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struct gk20a;
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struct channel_gk20a;
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struct fifo_gk20a;
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struct tsg_gk20a;
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int vgpu_init_fifo_setup_hw(struct gk20a *g);
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void vgpu_channel_bind(struct channel_gk20a *ch);
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void vgpu_channel_unbind(struct channel_gk20a *ch);
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int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch);
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void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch);
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void vgpu_channel_enable(struct channel_gk20a *ch);
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void vgpu_channel_disable(struct channel_gk20a *ch);
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int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
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u32 gpfifo_entries,
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unsigned long acquire_timeout, u32 flags);
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int vgpu_fifo_init_engine_info(struct fifo_gk20a *f);
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int vgpu_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch);
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int vgpu_fifo_preempt_tsg(struct gk20a *g, struct tsg_gk20a *tsg);
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int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
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struct channel_gk20a *ch,
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bool add, bool wait_for_finish);
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int vgpu_fifo_wait_engine_idle(struct gk20a *g);
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int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
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u32 id,
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u32 runlist_id,
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u32 new_level);
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int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice);
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int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
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u32 err_code, bool verbose);
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u32 vgpu_fifo_default_timeslice_us(struct gk20a *g);
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int vgpu_tsg_open(struct tsg_gk20a *tsg);
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void vgpu_tsg_release(struct tsg_gk20a *tsg);
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int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
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struct channel_gk20a *ch);
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int vgpu_tsg_unbind_channel(struct channel_gk20a *ch);
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int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
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int vgpu_enable_tsg(struct tsg_gk20a *tsg);
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int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, u32 mask);
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#endif
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