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13ca3c9a37
Read mask of GPC’s to boot only enabled GPC’s and discard floorswept GPC. Read GPC’s mask info need to send to SEC2 RTOS to bootstrap enabled GPC’s. JIRA NVGPU-5466 Change-Id: Id4ed7d4072730da8e128cd43af92a1a6b1aac8ad Signed-off-by: mkumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2394004 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Dinesh T <dt@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu/pmuif/cmn.h>
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#include <nvgpu/sec2/lsfm.h>
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#include <nvgpu/sec2/msg.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/sec2/cmd.h>
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#include <nvgpu/gr/config.h>
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#include <nvgpu/gr/gr_utils.h>
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/* Add code below to handle SEC2 RTOS commands */
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/* LSF's bootstrap command */
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static void sec2_handle_lsfm_boot_acr_msg(struct gk20a *g,
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struct nv_flcn_msg_sec2 *msg,
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void *param, u32 status)
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{
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bool *command_ack = param;
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nvgpu_log_fn(g, " ");
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nvgpu_sec2_dbg(g, "reply NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON");
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nvgpu_sec2_dbg(g, "flcn %d: error code = %x",
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msg->msg.acr.msg_flcn.falcon_id,
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msg->msg.acr.msg_flcn.error_code);
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*command_ack = true;
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}
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static void sec2_load_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
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u32 falcon_id, u32 flags)
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{
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struct nv_flcn_cmd_sec2 cmd;
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bool command_ack;
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int err = 0;
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size_t tmp_size;
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nvgpu_log_fn(g, " ");
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/* send message to load falcon */
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(void) memset(&cmd, 0, sizeof(struct nv_flcn_cmd_sec2));
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cmd.hdr.unit_id = NV_SEC2_UNIT_ACR;
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tmp_size = PMU_CMD_HDR_SIZE +
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sizeof(struct nv_sec2_acr_cmd_bootstrap_falcon);
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nvgpu_assert(tmp_size <= U64(U8_MAX));
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cmd.hdr.size = U8(tmp_size);
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cmd.cmd.acr.bootstrap_falcon.cmd_type =
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NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON;
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cmd.cmd.acr.bootstrap_falcon.flags = flags;
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cmd.cmd.acr.bootstrap_falcon.falcon_id = falcon_id;
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cmd.cmd.acr.bootstrap_falcon.falcon_instance =
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LSF_FALCON_INSTANCE_DEFAULT;
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cmd.cmd.acr.bootstrap_falcon.falcon_index_mask =
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LSF_FALCON_INDEX_MASK_DEFAULT;
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if (falcon_id == FALCON_ID_GPCCS) {
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cmd.cmd.acr.bootstrap_falcon.falcon_index_mask =
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nvgpu_gr_config_get_gpc_mask(nvgpu_gr_get_config_ptr(g));
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}
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nvgpu_sec2_dbg(g, "NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON : %x",
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falcon_id);
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command_ack = false;
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err = nvgpu_sec2_cmd_post(g, &cmd, PMU_COMMAND_QUEUE_HPQ,
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sec2_handle_lsfm_boot_acr_msg, &command_ack, U32_MAX);
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if (err != 0) {
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nvgpu_err(g, "command post failed");
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}
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err = nvgpu_sec2_wait_message_cond(sec2, nvgpu_get_poll_timeout(g),
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&command_ack, U8(true));
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if (err != 0) {
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nvgpu_err(g, "command ack receive failed");
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}
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}
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int nvgpu_sec2_bootstrap_ls_falcons(struct gk20a *g, struct nvgpu_sec2 *sec2,
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u32 falcon_id)
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{
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int err = 0;
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nvgpu_log_fn(g, " ");
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nvgpu_sec2_dbg(g, "Check SEC2 RTOS is ready else wait");
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err = nvgpu_sec2_wait_message_cond(&g->sec2, nvgpu_get_poll_timeout(g),
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&g->sec2.sec2_ready, U8(true));
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if (err != 0) {
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nvgpu_err(g, "SEC2 RTOS not ready yet, failed to bootstrap flcn %d",
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falcon_id);
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goto exit;
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}
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nvgpu_sec2_dbg(g, "LS flcn %d bootstrap, blocked call", falcon_id);
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sec2_load_ls_falcons(g, sec2, falcon_id,
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NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES);
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exit:
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nvgpu_sec2_dbg(g, "Done, err-%x", err);
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return err;
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}
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