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40397ac0c4
At present, for each resume cycle the driver sends the "nvgpu_cbc_op_clear" command to L2 cache controller, this causes the contents of the compression bit backing store to be cleared, and results in corrupting the metadata for all the compressible surfaces already allocated. Fix this by updating cbc.init function to be aware of resume state and not clear the compression bit backing store, instead issue "nvgpu_cbc_op_invalide" command, this should leave the backing store in a consistent state across suspend/resume cycles. The updated cbc.init HAL for gv11b is reusable acrosss multiple chips, hence remove unnecessary chip specific cbc.init HALs. Bug 3483688 Change-Id: I2de848a083436bc085ee98e438874214cb61261f Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2660075 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
40 lines
1.4 KiB
C
40 lines
1.4 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef CBC_TU104_H
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#define CBC_TU104_H
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#ifdef CONFIG_NVGPU_COMPRESSION
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#include <nvgpu/types.h>
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enum nvgpu_cbc_op;
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struct gk20a;
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struct nvgpu_cbc;
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int tu104_cbc_alloc_comptags(struct gk20a *g, struct nvgpu_cbc *cbc);
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int tu104_cbc_ctrl(struct gk20a *g, enum nvgpu_cbc_op op,
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u32 min, u32 max);
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#endif
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#endif
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