mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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9890a185e0
- Patch updates the ZBC table values as per the POR values for safety build. - Fix the color table default values initialization for standard build which was being done in floating point format for CROP while it should be in FB format. As per the documentation "CROP ZBC table should be programmed exactly the way the L2 table is programmed". Bug 3585766 Change-Id: I47d11b6a230189ee0c818f850d36b93c0aea0e54 Signed-off-by: prsethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2724935 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> GVS: Gerrit_Virtual_Submit
210 lines
7.8 KiB
C
210 lines
7.8 KiB
C
/*
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* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef ZBC_GA10B_H
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#define ZBC_GA10B_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_gr_zbc_table_indices;
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struct nvgpu_gr_zbc;
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void ga10b_gr_zbc_init_table_indices(struct gk20a *g,
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struct nvgpu_gr_zbc_table_indices *zbc_indices);
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void ga10b_gr_zbc_add_color(struct gk20a *g,
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struct nvgpu_gr_zbc_entry *color_val, u32 index);
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void ga10b_gr_zbc_load_static_table(struct gk20a *g,
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struct nvgpu_gr_zbc *zbc);
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#define NVGPU_ZBC_SET_COLOR_ATTR(tbl, ind, i) \
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{ \
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(tbl)[ind].color_ds[0] = (NVGPU_ZBC_CL_VAL_1_IND_##i); \
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(tbl)[ind].color_ds[1] = (NVGPU_ZBC_CL_VAL_2_IND_##i); \
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(tbl)[ind].color_ds[2] = (NVGPU_ZBC_CL_VAL_3_IND_##i); \
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(tbl)[ind].color_ds[3] = (NVGPU_ZBC_CL_VAL_4_IND_##i); \
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(tbl)[ind].color_l2[0] = (NVGPU_ZBC_CL_VAL_1_IND_##i); \
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(tbl)[ind].color_l2[1] = (NVGPU_ZBC_CL_VAL_2_IND_##i); \
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(tbl)[ind].color_l2[2] = (NVGPU_ZBC_CL_VAL_3_IND_##i); \
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(tbl)[ind].color_l2[3] = (NVGPU_ZBC_CL_VAL_4_IND_##i); \
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(tbl)[ind].ref_cnt = nvgpu_safe_add_u32((tbl)[ind].ref_cnt, 1U);\
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ind = nvgpu_safe_add_u32(ind, 1U); \
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}
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#define NVGPU_ZBC_CL_VAL_1_IND_1 0xff000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_1 0xff000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_1 0xff000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_1 0xff000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_2 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_2 0x00000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_2 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_2 0x00000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_3 0xffffffffU
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#define NVGPU_ZBC_CL_VAL_2_IND_3 0xffffffffU
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#define NVGPU_ZBC_CL_VAL_3_IND_3 0xffffffffU
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#define NVGPU_ZBC_CL_VAL_4_IND_3 0xffffffffU
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#ifndef CONFIG_NVGPU_NON_FUSA
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#define NVGPU_ZBC_CL_VAL_1_IND_4 0x7f000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_4 0x7f000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_4 0x7f000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_4 0x7f000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_5 0x40000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_5 0x40000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_5 0x40000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_5 0x40000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_6 0xbf000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_6 0xbf000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_6 0xbf000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_6 0xbf000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_7 0xff0000ffU
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#define NVGPU_ZBC_CL_VAL_2_IND_7 0xff0000ffU
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#define NVGPU_ZBC_CL_VAL_3_IND_7 0xff0000ffU
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#define NVGPU_ZBC_CL_VAL_4_IND_7 0xff0000ffU
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#define NVGPU_ZBC_CL_VAL_1_IND_8 0x00ffffffU
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#define NVGPU_ZBC_CL_VAL_2_IND_8 0x00ffffffU
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#define NVGPU_ZBC_CL_VAL_3_IND_8 0x00ffffffU
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#define NVGPU_ZBC_CL_VAL_4_IND_8 0x00ffffffU
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#define NVGPU_ZBC_CL_VAL_1_IND_9 0x7fffffffU
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#define NVGPU_ZBC_CL_VAL_2_IND_9 0x7fffffffU
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#define NVGPU_ZBC_CL_VAL_3_IND_9 0x7fffffffU
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#define NVGPU_ZBC_CL_VAL_4_IND_9 0x7fffffffU
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#define NVGPU_ZBC_CL_VAL_1_IND_10 0xffff0000U
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#define NVGPU_ZBC_CL_VAL_2_IND_10 0xffff0000U
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#define NVGPU_ZBC_CL_VAL_3_IND_10 0xffff0000U
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#define NVGPU_ZBC_CL_VAL_4_IND_10 0xffff0000U
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#define NVGPU_ZBC_CL_VAL_1_IND_11 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_11 0x3c000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_11 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_11 0x3c000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_12 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_12 0x38000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_12 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_12 0x38000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_13 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_13 0x34000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_13 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_13 0x34000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_14 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_14 0x3a000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_14 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_14 0x3a000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_15 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_15 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_3_IND_15 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_15 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_1_IND_16 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_2_IND_16 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_3_IND_16 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_4_IND_16 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_1_IND_17 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_2_IND_17 0x00003c00U
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#define NVGPU_ZBC_CL_VAL_3_IND_17 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_4_IND_17 0x00003c00U
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#define NVGPU_ZBC_CL_VAL_1_IND_18 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_2_IND_18 0x38003c00U
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#define NVGPU_ZBC_CL_VAL_3_IND_18 0x3c003c00U
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#define NVGPU_ZBC_CL_VAL_4_IND_18 0x38003c00U
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#define NVGPU_ZBC_CL_VAL_1_IND_19 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_19 0x00000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_19 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_19 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_1_IND_20 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_20 0x00000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_20 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_20 0x3f000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_21 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_21 0x00000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_21 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_21 0x3e800000U
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#define NVGPU_ZBC_CL_VAL_1_IND_22 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_22 0x00000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_22 0x00000000U
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#define NVGPU_ZBC_CL_VAL_4_IND_22 0x3f400000U
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#define NVGPU_ZBC_CL_VAL_1_IND_23 0x00000000U
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#define NVGPU_ZBC_CL_VAL_2_IND_23 0x00000000U
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#define NVGPU_ZBC_CL_VAL_3_IND_23 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_4_IND_23 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_1_IND_24 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_2_IND_24 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_3_IND_24 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_4_IND_24 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_1_IND_25 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_2_IND_25 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_3_IND_25 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_4_IND_25 0x00000000U
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#define NVGPU_ZBC_CL_VAL_1_IND_26 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_2_IND_26 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_3_IND_26 0x3f800000U
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#define NVGPU_ZBC_CL_VAL_4_IND_26 0x3f000000U
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#endif
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#define NVGPU_ZBC_SET_DEPTH_ATTR(tbl, i) \
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{ \
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(tbl).depth = (NVGPU_ZBC_DPTH_##i); \
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(tbl).format = (NVGPU_ZBC_DPTH_FMT_##i); \
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(tbl).ref_cnt = nvgpu_safe_add_u32((tbl).ref_cnt, 1U); \
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}
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#define NVGPU_ZBC_DPTH_1 0x3f800000U
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#define NVGPU_ZBC_DPTH_FMT_1 GR_ZBC_Z_FMT_VAL_FP32
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#define NVGPU_ZBC_DPTH_2 0U
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#define NVGPU_ZBC_DPTH_FMT_2 GR_ZBC_Z_FMT_VAL_FP32
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#define NVGPU_ZBC_SET_STENCIL_ATTR(tbl, i) \
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{ \
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(tbl).stencil = (NVGPU_ZBC_SCIL_##i); \
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(tbl).format = (NVGPU_ZBC_SCIL_FMT_##i); \
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(tbl).ref_cnt = nvgpu_safe_add_u32((tbl).ref_cnt, 1U); \
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}
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#define NVGPU_ZBC_SCIL_1 0x00000000U
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#define NVGPU_ZBC_SCIL_FMT_1 GR_ZBC_STENCIL_CLEAR_FMT_U8
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#define NVGPU_ZBC_SCIL_2 0x00000001U
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#define NVGPU_ZBC_SCIL_FMT_2 GR_ZBC_STENCIL_CLEAR_FMT_U8
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#define NVGPU_ZBC_SCIL_3 0xffU
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#define NVGPU_ZBC_SCIL_FMT_3 GR_ZBC_STENCIL_CLEAR_FMT_U8
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#endif /* ZBC_GA10B_H */
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