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git://nv-tegra.nvidia.com/linux-nvgpu.git
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e81a36e56a
It's preparing to add bellow CFLAGS:
-Werror -Wall -Wextra \
-Wmissing-braces -Wpointer-arith -Wundef \
-Wconversion -Wsign-conversion \
-Wformat-security \
-Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough
Jira GVSCI-11640
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia16ef186da1e97badff9dd0bf8cbd6700dd77b15
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555057
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
115 lines
4.2 KiB
C
115 lines
4.2 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gr/zbc.h>
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#include "zbc_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
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void gp10b_gr_zbc_init_table_indices(struct gk20a *g,
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struct nvgpu_gr_zbc_table_indices *zbc_indices)
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{
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(void)g;
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/* Color indices */
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zbc_indices->min_color_index = NVGPU_GR_ZBC_STARTOF_TABLE;
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zbc_indices->max_color_index = gr_gpcs_swdx_dss_zbc_color_r__size_1_v();
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/* Depth indices */
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zbc_indices->min_depth_index = NVGPU_GR_ZBC_STARTOF_TABLE;
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zbc_indices->max_depth_index = gr_gpcs_swdx_dss_zbc_z__size_1_v();
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/* Stencil indices */
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zbc_indices->min_stencil_index = 0U;
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zbc_indices->max_stencil_index = 0U;
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}
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u32 gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g)
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{
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(void)g;
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return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r();
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}
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u32 gp10b_gr_zbc_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g)
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{
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(void)g;
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return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r();
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}
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void gp10b_gr_zbc_add_color(struct gk20a *g,
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struct nvgpu_gr_zbc_entry *color_val, u32 index)
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{
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u32 zbc_c;
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u32 zbc_c_format_reg;
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u32 hw_index = nvgpu_safe_sub_u32(index, NVGPU_GR_ZBC_STARTOF_TABLE);
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nvgpu_log(g, gpu_dbg_zbc, "adding color at index %u", index);
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nvgpu_log(g, gpu_dbg_zbc, "color[0-3]: 0x%08x 0x%08x 0x%08x 0x%08x",
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 0),
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 1),
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 2),
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 3));
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nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_r_r(hw_index),
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 0));
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nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_g_r(hw_index),
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 1));
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nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_b_r(hw_index),
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 2));
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nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_a_r(hw_index),
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nvgpu_gr_zbc_get_entry_color_ds(color_val, 3));
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/* Update format register */
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zbc_c_format_reg = g->ops.gr.zbc.get_gpcs_swdx_dss_zbc_c_format_reg(g);
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zbc_c = nvgpu_readl(g, zbc_c_format_reg + (hw_index & ~3U));
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zbc_c &= ~(U32(0x7f) << ((hw_index % 4U) * 7U));
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zbc_c |= nvgpu_gr_zbc_get_entry_format(color_val) <<
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((hw_index % 4U) * 7U);
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nvgpu_writel_loop(g, zbc_c_format_reg + (hw_index & ~3U), zbc_c);
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}
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void gp10b_gr_zbc_add_depth(struct gk20a *g,
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struct nvgpu_gr_zbc_entry *depth_val, u32 index)
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{
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u32 zbc_z;
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u32 zbc_z_format_reg;
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u32 hw_index = nvgpu_safe_sub_u32(index, NVGPU_GR_ZBC_STARTOF_TABLE);
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nvgpu_log(g, gpu_dbg_zbc, "adding depth at index %u", index);
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nvgpu_log(g, gpu_dbg_zbc, "depth: 0x%08x",
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nvgpu_gr_zbc_get_entry_depth(depth_val));
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nvgpu_writel(g, gr_gpcs_swdx_dss_zbc_z_r(hw_index),
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nvgpu_gr_zbc_get_entry_depth(depth_val));
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/* Update format register */
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zbc_z_format_reg = g->ops.gr.zbc.get_gpcs_swdx_dss_zbc_z_format_reg(g);
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zbc_z = nvgpu_readl(g, zbc_z_format_reg + (hw_index & ~3U));
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zbc_z &= ~(U32(0x7f) << ((hw_index % 4U) * 7U));
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zbc_z |= nvgpu_gr_zbc_get_entry_format(depth_val) <<
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(hw_index % 4U) * 7U;
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nvgpu_writel(g, zbc_z_format_reg + (hw_index & ~3U), zbc_z);
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}
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