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linux-nvgpu/drivers/gpu/nvgpu/Makefile.sources
Thomas Fleury c7b41f106d gpu: nvgpu: add CONFIG_NVGPU_RECOVERY 
Add CONFIG_NVGPU_RECOVERY in order to conditionally compile
recovery code. This code will be removed from safety build
when sw quiesce state is implemented, and negative tests are
disabled or modified such that they do not expect recovery
to happen.

Added static inline functions for recovery handlers, when
CONFIG_NVGPU_RECOVERY is not defined. These inline functions
can later be wired to the sw quiesce functions.

Also moved gv11b recovery code to non-fusa, as it will ultimately
be removed from safety build.

Jira NVGPU-3871

Change-Id: Ia705b059fab6120899c7e15082f2a0f51ff51dc9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166074
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-08-07 08:25:57 -07:00

643 lines
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# -*- mode: makefile -*-
#
# Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
srcs :=
ifdef NVGPU_POSIX
srcs += os/posix/nvgpu.c \
os/posix/posix-io.c \
os/posix/posix-nvgpu_mem.c \
os/posix/posix-dma.c \
os/posix/posix-vm.c \
os/posix/firmware.c \
os/posix/soc.c \
os/posix/error_notifier.c \
os/posix/fuse.c \
os/posix/posix-channel.c \
os/posix/posix-tsg.c \
os/posix/stubs.c \
os/posix/posix-nvhost.c \
os/posix/posix-vgpu.c \
os/posix/posix-dt.c
ifdef CONFIG_NVGPU_FECS_TRACE
srcs += os/posix/fecs_trace_posix.c
endif
ifeq ($(CONFIG_NVGPU_CLK_ARB),1)
srcs += os/posix/posix-clk_arb.c
endif
ifdef CONFIG_NVGPU_NVLINK
srcs += os/posix/posix-nvlink.c
endif
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += os/posix/posix-comptags.c
endif
ifeq ($(CONFIG_NVGPU_LOGGING),1)
srcs += os/posix/log.c
endif
ifeq ($(CONFIG_NVGPU_SIM),1)
srcs += os/posix/posix-sim.c
endif
ifeq ($(CONFIG_NVGPU_DGPU),1)
srcs += os/posix/posix-vidmem.c
endif
endif
# POSIX sources shared between the POSIX and QNX builds.
srcs += os/posix/bug.c \
os/posix/rwsem.c \
os/posix/timers.c \
os/posix/cond.c \
os/posix/lock.c \
os/posix/thread.c \
os/posix/bsearch.c \
os/posix/os_sched.c \
os/posix/bitmap.c \
os/posix/kmem.c
srcs += common/utils/assert.c \
common/utils/enabled.c \
common/utils/rbtree.c \
common/utils/string.c \
common/utils/worker.c \
common/init/nvgpu_init.c \
common/mm/allocators/nvgpu_allocator.c \
common/mm/allocators/bitmap_allocator.c \
common/mm/allocators/buddy_allocator.c \
common/mm/allocators/lockless_allocator.c \
common/mm/gmmu/page_table.c \
common/mm/gmmu/pd_cache.c \
common/mm/as.c \
common/mm/vm.c \
common/mm/vm_area.c \
common/mm/nvgpu_mem.c \
common/mm/nvgpu_sgt.c \
common/mm/mm.c \
common/mm/dma.c \
common/therm/therm.c \
common/ltc/ltc.c \
common/fbp/fbp.c \
common/io/io.c \
common/ecc.c \
common/falcon/falcon.c \
common/falcon/falcon_sw_gk20a.c \
common/gr/gr.c \
common/gr/gr_utils.c \
common/gr/gr_intr.c \
common/gr/global_ctx.c \
common/gr/subctx.c \
common/gr/ctx.c \
common/gr/gr_falcon.c \
common/gr/gr_config.c \
common/gr/gr_setup.c \
common/gr/obj_ctx.c \
common/gr/fs_state.c \
common/netlist/netlist.c \
common/pmu/pmu.c \
common/acr/acr.c \
common/acr/acr_wpr.c \
common/acr/acr_blob_alloc.c \
common/acr/acr_blob_construct_v1.c \
common/acr/acr_bootstrap.c \
common/acr/acr_sw_gv11b.c \
common/ptimer/ptimer.c \
common/sync/channel_sync.c \
common/sync/channel_sync_syncpt.c \
common/power_features/power_features.c \
common/power_features/cg/cg.c \
common/fifo/preempt.c \
common/fifo/channel.c \
common/fifo/fifo.c \
common/fifo/pbdma.c \
common/fifo/tsg.c \
common/fifo/runlist.c \
common/fifo/engine_status.c \
common/fifo/engines.c \
common/fifo/pbdma_status.c \
common/mc/mc.c \
hal/init/hal_gv11b.c \
hal/init/hal_gv11b_litter.c \
hal/init/hal_init.c \
hal/power_features/cg/gv11b_gating_reglist.c \
hal/fifo/runlist_fifo_gk20a.c \
hal/fifo/runlist_fifo_gv11b.c \
hal/fifo/runlist_ram_gk20a.c \
hal/fifo/userd_gk20a.c \
hal/sync/syncpt_cmdbuf_gv11b.c
# Source files below are functionaly safe (FuSa) and must always be included.
srcs += hal/mm/mm_gv11b_fusa.c \
hal/mm/mm_gp10b_fusa.c \
hal/mm/gmmu/gmmu_gv11b_fusa.c \
hal/mm/gmmu/gmmu_gp10b_fusa.c \
hal/mm/gmmu/gmmu_gk20a_fusa.c \
hal/mm/gmmu/gmmu_gm20b_fusa.c \
hal/mm/cache/flush_gk20a_fusa.c \
hal/mm/cache/flush_gv11b_fusa.c \
hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c \
hal/ltc/intr/ltc_intr_gp10b_fusa.c \
hal/ltc/intr/ltc_intr_gv11b_fusa.c \
hal/bus/bus_gk20a_fusa.c \
hal/bus/bus_gm20b_fusa.c \
hal/bus/bus_gp10b_fusa.c \
hal/ce/ce_gp10b_fusa.c \
hal/ce/ce_gv11b_fusa.c \
hal/class/class_gm20b_fusa.c \
hal/class/class_gp10b_fusa.c \
hal/class/class_gv11b_fusa.c \
hal/falcon/falcon_gk20a_fusa.c \
hal/fb/fb_gm20b_fusa.c \
hal/fb/fb_gv11b_fusa.c \
hal/fb/fb_mmu_fault_gv11b_fusa.c \
hal/fb/intr/fb_intr_ecc_gv11b_fusa.c \
hal/fb/intr/fb_intr_gv11b_fusa.c \
hal/fifo/channel_gk20a_fusa.c \
hal/fifo/channel_gm20b_fusa.c \
hal/fifo/channel_gv11b_fusa.c \
hal/fifo/ctxsw_timeout_gv11b_fusa.c \
hal/fifo/engine_status_gm20b_fusa.c \
hal/fifo/engine_status_gv100_fusa.c \
hal/fifo/engines_gp10b_fusa.c \
hal/fifo/engines_gv11b_fusa.c \
hal/fifo/fifo_gk20a_fusa.c \
hal/fifo/fifo_gv11b_fusa.c \
hal/fifo/fifo_intr_gk20a_fusa.c \
hal/fifo/fifo_intr_gv11b_fusa.c \
hal/fifo/pbdma_gm20b_fusa.c \
hal/fifo/pbdma_gp10b_fusa.c \
hal/fifo/pbdma_gv11b_fusa.c \
hal/fifo/pbdma_status_gm20b_fusa.c \
hal/fifo/preempt_gv11b_fusa.c \
hal/fifo/ramfc_gp10b_fusa.c \
hal/fifo/ramfc_gv11b_fusa.c \
hal/fifo/ramin_gk20a_fusa.c \
hal/fifo/ramin_gm20b_fusa.c \
hal/fifo/ramin_gp10b_fusa.c \
hal/fifo/ramin_gv11b_fusa.c \
hal/fifo/runlist_fifo_gk20a_fusa.c \
hal/fifo/runlist_fifo_gv11b_fusa.c \
hal/fifo/runlist_ram_gv11b_fusa.c \
hal/fifo/tsg_gv11b_fusa.c \
hal/fifo/usermode_gv11b_fusa.c \
hal/fuse/fuse_gm20b_fusa.c \
hal/fuse/fuse_gp10b_fusa.c \
hal/gr/config/gr_config_gm20b_fusa.c \
hal/gr/config/gr_config_gv100_fusa.c \
hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c \
hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c \
hal/gr/ctxsw_prog/ctxsw_prog_gv11b_fusa.c \
hal/gr/ecc/ecc_gv11b_fusa.c \
hal/gr/falcon/gr_falcon_gm20b_fusa.c \
hal/gr/falcon/gr_falcon_gp10b_fusa.c \
hal/gr/falcon/gr_falcon_gv11b_fusa.c \
hal/gr/init/gr_init_gm20b_fusa.c \
hal/gr/init/gr_init_gp10b_fusa.c \
hal/gr/init/gr_init_gv11b_fusa.c \
hal/gr/intr/gr_intr_gm20b_fusa.c \
hal/gr/intr/gr_intr_gp10b_fusa.c \
hal/gr/intr/gr_intr_gv11b_fusa.c \
hal/ltc/ltc_gm20b_fusa.c \
hal/ltc/ltc_gp10b_fusa.c \
hal/ltc/ltc_gv11b_fusa.c \
hal/mc/mc_gm20b_fusa.c \
hal/mc/mc_gp10b_fusa.c \
hal/mc/mc_gv11b_fusa.c \
hal/netlist/netlist_gv11b_fusa.c \
hal/pmu/pmu_gv11b_fusa.c \
hal/priv_ring/priv_ring_gm20b_fusa.c \
hal/priv_ring/priv_ring_gp10b_fusa.c \
hal/ptimer/ptimer_gk20a_fusa.c \
hal/sync/syncpt_cmdbuf_gv11b_fusa.c \
hal/therm/therm_gm20b_fusa.c \
hal/therm/therm_gv11b_fusa.c \
hal/top/top_gm20b_fusa.c \
hal/top/top_gp10b_fusa.c \
hal/top/top_gv11b_fusa.c
# Source files below are not guaranteed to be functionaly safe (FuSa) and are
# only included in the normal build.
ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
srcs += hal/init/hal_gp10b.c \
hal/init/hal_gp10b_litter.c \
hal/init/hal_gm20b.c \
hal/init/hal_gm20b_litter.c \
hal/mm/mm_gm20b.c \
hal/mm/mm_gk20a.c \
hal/mm/gmmu/gmmu_gk20a.c \
hal/mm/gmmu/gmmu_gm20b.c \
hal/mc/mc_gm20b.c \
hal/mc/mc_gp10b.c \
hal/bus/bus_gk20a.c \
hal/class/class_gm20b.c \
hal/clk/clk_gm20b.c \
hal/falcon/falcon_gk20a.c \
hal/gr/config/gr_config_gm20b.c \
hal/gr/ecc/ecc_gp10b.c \
hal/gr/init/gr_init_gm20b.c \
hal/gr/init/gr_init_gp10b.c \
hal/gr/init/gr_init_gv11b.c \
hal/gr/intr/gr_intr_gm20b.c \
hal/gr/intr/gr_intr_gp10b.c \
hal/gr/falcon/gr_falcon_gm20b.c \
hal/priv_ring/priv_ring_gm20b.c \
hal/power_features/cg/gm20b_gating_reglist.c \
hal/power_features/cg/gp10b_gating_reglist.c \
hal/power_features/cg/gp106_gating_reglist.c \
hal/ce/ce2_gk20a.c \
hal/therm/therm_gm20b.c \
hal/therm/therm_gp10b.c \
hal/ltc/ltc_gm20b.c \
hal/ltc/ltc_gp10b.c \
hal/ltc/ltc_gv11b.c \
hal/ltc/intr/ltc_intr_gm20b.c \
hal/ltc/intr/ltc_intr_gp10b.c \
hal/fb/fb_gp10b.c \
hal/fb/fb_gp106.c \
hal/fb/fb_gm20b.c \
hal/fb/fb_gv11b.c \
hal/fuse/fuse_gm20b.c \
hal/fifo/fifo_gk20a.c \
hal/fifo/preempt_gk20a.c \
hal/fifo/engines_gm20b.c \
hal/fifo/pbdma_gm20b.c \
hal/fifo/pbdma_gp10b.c \
hal/fifo/engine_status_gm20b.c \
hal/fifo/ramfc_gk20a.c \
hal/fifo/ramfc_gp10b.c \
hal/fifo/ramin_gk20a.c \
hal/fifo/channel_gk20a.c \
hal/fifo/channel_gm20b.c \
hal/fifo/tsg_gk20a.c \
hal/fifo/fifo_intr_gk20a.c \
hal/fifo/mmu_fault_gk20a.c \
hal/fifo/mmu_fault_gm20b.c \
hal/fifo/mmu_fault_gp10b.c \
hal/fifo/ctxsw_timeout_gk20a.c \
hal/netlist/netlist_gm20b.c \
hal/netlist/netlist_gp10b.c \
hal/sync/syncpt_cmdbuf_gk20a.c \
hal/pmu/pmu_gv11b.c \
hal/top/top_gm20b.c \
hal/top/top_gp106.c \
hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c \
hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c \
hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c
endif
ifeq ($(CONFIG_NVGPU_CLK_ARB),1)
srcs += \
common/clk_arb/clk_arb.c \
common/clk_arb/clk_arb_gp10b.c
endif
ifeq ($(CONFIG_NVGPU_ACR_LEGACY),1)
srcs += \
common/acr/acr_blob_construct_v0.c \
common/acr/acr_sw_gm20b.c \
common/acr/acr_sw_gp10b.c
endif
ifeq ($(CONFIG_NVGPU_ENGINE_QUEUE),1)
srcs += common/engine_queues/engine_mem_queue.c \
common/engine_queues/engine_dmem_queue.c \
common/engine_queues/engine_emem_queue.c \
common/engine_queues/engine_fb_queue.c
endif
ifeq ($(CONFIG_NVGPU_GRAPHICS),1)
srcs += common/gr/zbc.c \
common/gr/zcull.c \
hal/gr/zbc/zbc_gm20b.c \
hal/gr/zbc/zbc_gp10b.c \
hal/gr/zbc/zbc_gv11b.c \
hal/gr/zcull/zcull_gm20b.c \
hal/gr/zcull/zcull_gv11b.c
endif
ifeq ($(CONFIG_NVGPU_DEBUGGER),1)
srcs += common/debugger.c \
common/regops/regops.c \
common/gr/hwpm_map.c \
common/perf/perfbuf.c \
hal/regops/regops_gv11b.c \
hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c \
hal/gr/hwpm_map/hwpm_map_gv100.c \
hal/ltc/ltc_gm20b_dbg.c \
hal/perf/perf_gv11b.c \
hal/gr/gr/gr_gk20a.c \
hal/gr/gr/gr_gm20b.c \
hal/gr/gr/gr_gp10b.c \
hal/gr/gr/gr_gv11b.c \
hal/gr/gr/gr_gv100.c \
hal/gr/gr/gr_tu104.c
ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
srcs += hal/regops/regops_gm20b.c \
hal/regops/regops_gp10b.c \
hal/regops/regops_gv100.c \
hal/regops/regops_tu104.c \
hal/perf/perf_gm20b.c
endif
endif
ifeq ($(CONFIG_NVGPU_CE),1)
srcs += common/ce/ce.c
endif
ifeq ($(CONFIG_NVGPU_KERNEL_MODE_SUBMIT),1)
srcs += common/fifo/submit.c
endif
ifeq ($(CONFIG_NVGPU_SW_SEMAPHORE),1)
srcs += common/semaphore/semaphore_sea.c \
common/semaphore/semaphore_pool.c \
common/semaphore/semaphore_hw.c \
common/semaphore/semaphore.c \
common/sync/channel_sync_semaphore.c \
hal/sync/sema_cmdbuf_gk20a.c \
hal/sync/sema_cmdbuf_gv11b.c
endif
ifeq ($(CONFIG_NVGPU_USERD),1)
srcs += common/fifo/userd.c \
hal/fifo/userd_gv11b.c
endif
ifeq ($(CONFIG_NVGPU_RECOVERY),1)
srcs += common/rc/rc.c \
hal/rc/rc_gv11b.c
ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
srcs += hal/rc/rc_gk20a.c
endif
endif
ifeq ($(CONFIG_NVGPU_FENCE),1)
srcs += common/fence/fence.c
endif
ifeq ($(CONFIG_NVGPU_FECS_TRACE),1)
srcs += common/gr/fecs_trace.c \
hal/gr/fecs_trace/fecs_trace_gm20b.c \
hal/gr/fecs_trace/fecs_trace_gv11b.c
ifeq ($(CONFIG_NVGPU_IGPU_VIRT),1)
srcs += common/vgpu/gr/fecs_trace_vgpu.c
endif
endif
ifeq ($(CONFIG_NVGPU_CYCLESTATS),1)
srcs += common/perf/cyclestats_snapshot.c \
common/cyclestats/cyclestats.c
ifeq ($(CONFIG_NVGPU_IGPU_VIRT),1)
srcs += common/vgpu/perf/cyclestats_snapshot_vgpu.c
endif
endif
# POSIX file used for unit testing for both qnx and linux
ifdef NVGPU_FAULT_INJECTION_ENABLEMENT
srcs += os/posix/posix-fault-injection.c
endif
ifeq ($(CONFIG_NVGPU_LS_PMU),1)
# Add LS PMU files which are required for normal build
srcs += \
common/pmu/boardobj/boardobj.c \
common/pmu/boardobj/boardobjgrp.c \
common/pmu/boardobj/boardobjgrpmask.c \
common/pmu/boardobj/boardobjgrp_e255.c \
common/pmu/boardobj/boardobjgrp_e32.c \
common/pmu/clk/clk.c \
common/pmu/clk/clk_domain.c \
common/pmu/clk/clk_freq_domain.c \
common/pmu/clk/clk_fll.c \
common/pmu/clk/clk_freq_controller.c \
common/pmu/clk/clk_prog.c \
common/pmu/clk/clk_vf_point.c \
common/pmu/clk/clk_vin.c \
common/pmu/fw/fw.c \
common/pmu/fw/fw_ver_ops.c \
common/pmu/fw/fw_ns_bootstrap.c \
common/pmu/ipc/pmu_cmd.c \
common/pmu/ipc/pmu_msg.c \
common/pmu/ipc/pmu_queue.c \
common/pmu/ipc/pmu_seq.c \
common/pmu/lpwr/lpwr.c \
common/pmu/lpwr/rppg.c \
common/pmu/lsfm/lsfm.c \
common/pmu/lsfm/lsfm_sw_gm20b.c \
common/pmu/lsfm/lsfm_sw_gp10b.c \
common/pmu/lsfm/lsfm_sw_gv100.c \
common/pmu/lsfm/lsfm_sw_tu104.c \
common/pmu/perf/pmu_perf.c \
common/pmu/perf/vfe_equ.c \
common/pmu/perf/vfe_var.c \
common/pmu/perf/perf_gv100.c \
common/pmu/perf/perf_ps35.c \
common/pmu/perf/perf_pstate.c \
common/pmu/perf/change_seq.c \
common/pmu/perfmon/pmu_perfmon.c \
common/pmu/perfmon/pmu_perfmon_sw_gm20b.c \
common/pmu/perfmon/pmu_perfmon_sw_gv11b.c \
common/pmu/pg/pg_sw_gm20b.c \
common/pmu/pg/pg_sw_gp10b.c \
common/pmu/pg/pg_sw_gp106.c \
common/pmu/pg/pg_sw_gv11b.c \
common/pmu/pg/pmu_pg.c \
common/pmu/pg/pmu_aelpg.c \
common/pmu/pmgr/pmgr.c \
common/pmu/pmgr/pmgrpmu.c \
common/pmu/pmgr/pwrdev.c \
common/pmu/pmgr/pwrmonitor.c \
common/pmu/pmgr/pwrpolicy.c \
common/pmu/super_surface/super_surface.c \
common/pmu/therm/thrm.c \
common/pmu/therm/thrmchannel.c \
common/pmu/therm/thrmdev.c \
common/pmu/therm/thrmpmu.c \
common/pmu/volt/volt_dev.c \
common/pmu/volt/volt_pmu.c \
common/pmu/volt/volt_policy.c \
common/pmu/volt/volt_rail.c \
common/pmu/pmu_allocator.c \
common/pmu/pmu_debug.c \
common/pmu/pmu_mutex.c \
common/pmu/pmu_pstate.c \
hal/therm/therm_tu104.c \
hal/pmu/pmu_gk20a.c \
hal/pmu/pmu_gm20b.c \
hal/pmu/pmu_gp10b.c \
hal/pmu/pmu_tu104.c
ifeq ($(CONFIG_NVGPU_CLK_ARB),1)
srcs += common/clk_arb/clk_arb_gv100.c
endif
endif
ifeq ($(CONFIG_NVGPU_POWER_PG),1)
srcs += common/power_features/pg/pg.c
endif
ifeq ($(CONFIG_NVGPU_IGPU_VIRT),1)
srcs += common/vgpu/init/init_vgpu.c \
common/vgpu/ivc/comm_vgpu.c \
common/vgpu/intr/intr_vgpu.c \
common/vgpu/ptimer/ptimer_vgpu.c \
common/vgpu/fifo/fifo_vgpu.c \
common/vgpu/fifo/channel_vgpu.c \
common/vgpu/fifo/tsg_vgpu.c \
common/vgpu/fifo/engines_vgpu.c \
common/vgpu/fifo/preempt_vgpu.c \
common/vgpu/fifo/runlist_vgpu.c \
common/vgpu/fifo/ramfc_vgpu.c \
common/vgpu/perf/perf_vgpu.c \
common/vgpu/mm/mm_vgpu.c \
common/vgpu/mm/vm_vgpu.c \
common/vgpu/gr/gr_vgpu.c \
common/vgpu/gr/ctx_vgpu.c \
common/vgpu/gr/subctx_vgpu.c \
common/vgpu/clk_vgpu.c \
common/vgpu/debugger_vgpu.c \
common/vgpu/ltc/ltc_vgpu.c \
common/vgpu/fbp/fbp_vgpu.c \
common/vgpu/ce_vgpu.c \
hal/vgpu/init/init_hal_vgpu.c \
hal/vgpu/init/vgpu_hal_gv11b.c \
hal/vgpu/init/vgpu_hal_gp10b.c \
hal/vgpu/fifo/fifo_gv11b_vgpu.c \
hal/vgpu/sync/syncpt_cmdbuf_gv11b_vgpu.c
ifeq ($(CONFIG_NVGPU_USERD),1)
srcs += common/vgpu/fifo/userd_vgpu.c
endif
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += common/vgpu/cbc/cbc_vgpu.c
endif
endif
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += common/mm/comptags.c \
common/cbc/cbc.c \
hal/cbc/cbc_gm20b.c \
hal/cbc/cbc_gp10b.c \
hal/cbc/cbc_gv11b.c
endif
ifeq ($(CONFIG_NVGPU_NVLINK),1)
srcs += common/vbios/nvlink_bios.c \
common/nvlink/probe.c \
common/nvlink/init/device_reginit.c \
common/nvlink/init/device_reginit_gv100.c \
common/nvlink/intr_and_err_handling_gv100.c \
common/nvlink/minion.c \
common/nvlink/link_mode_transitions.c \
common/nvlink/nvlink_gv100.c \
common/nvlink/nvlink_tu104.c \
common/nvlink/nvlink.c \
hal/nvlink/minion_gv100.c \
hal/nvlink/minion_tu104.c \
hal/nvlink/link_mode_transitions_gv100.c \
hal/nvlink/link_mode_transitions_tu104.c
endif
ifeq ($(CONFIG_NVGPU_DGPU),1)
srcs += common/sec2/sec2.c \
common/sec2/sec2_allocator.c \
common/sec2/sec2_lsfm.c \
common/sec2/ipc/sec2_cmd.c \
common/sec2/ipc/sec2_msg.c \
common/sec2/ipc/sec2_queue.c \
common/sec2/ipc/sec2_seq.c \
common/vbios/bios.c \
common/vbios/bios_sw_gv100.c \
common/vbios/bios_sw_tu104.c \
common/falcon/falcon_sw_tu104.c \
common/acr/acr_sw_tu104.c \
common/mm/allocators/page_allocator.c \
common/mm/vidmem.c \
common/pramin.c \
hal/mm/mm_gv100.c \
hal/mm/mm_tu104.c \
hal/mc/mc_gv100.c \
hal/mc/mc_tu104.c \
hal/bus/bus_gv100.c \
hal/bus/bus_tu104.c \
hal/ce/ce_tu104.c \
hal/class/class_tu104.c \
hal/clk/clk_tu104.c \
hal/gr/ecc/ecc_tu104.c \
hal/gr/init/gr_init_gv100.c \
hal/gr/init/gr_init_tu104.c \
hal/gr/intr/gr_intr_tu104.c \
hal/fbpa/fbpa_tu104.c \
hal/init/hal_tu104.c \
hal/init/hal_tu104_litter.c \
hal/power_features/cg/gv100_gating_reglist.c \
hal/power_features/cg/tu104_gating_reglist.c \
hal/ltc/ltc_tu104.c \
hal/fb/fb_gv100.c \
hal/fb/fb_tu104.c \
hal/fb/fb_mmu_fault_tu104.c \
hal/fb/intr/fb_intr_gv100.c \
hal/fb/intr/fb_intr_tu104.c \
hal/func/func_tu104.c \
hal/fifo/fifo_tu104.c \
hal/fifo/usermode_tu104.c \
hal/fifo/pbdma_tu104.c \
hal/fifo/ramfc_tu104.c \
hal/fifo/ramin_tu104.c \
hal/fifo/channel_gv100.c \
hal/fifo/runlist_ram_tu104.c \
hal/fifo/runlist_fifo_gv100.c \
hal/fifo/runlist_fifo_tu104.c \
hal/fifo/fifo_intr_gv100.c \
hal/fuse/fuse_gp106.c \
hal/netlist/netlist_gv100.c \
hal/netlist/netlist_tu104.c \
hal/nvdec/nvdec_gp106.c \
hal/nvdec/nvdec_tu104.c \
hal/gsp/gsp_tu104.c \
hal/sec2/sec2_tu104.c \
hal/pramin/pramin_gp10b.c \
hal/pramin/pramin_gv100.c \
hal/pramin/pramin_init.c \
hal/pramin/pramin_tu104.c \
hal/bios/bios_tu104.c \
hal/top/top_gv100.c \
hal/xve/xve_gp106.c
ifeq ($(CONFIG_NVGPU_COMPRESSION),1)
srcs += hal/cbc/cbc_tu104.c
endif
endif
ifeq ($(CONFIG_NVGPU_SIM),1)
srcs += common/sim/sim.c \
common/sim/sim_pci.c \
common/sim/sim_netlist.c
endif
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