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e364102f9a
Move GFXP related code under CONFIG_NVGPU_GRAPHICS flag. Keep the NVGPU_PREEMPTION_MODE_GRAPHICS_WFI support. JIRA NVGPU-3415 Change-Id: Ie690ac66df4b94eb113a5898d94a892fe0ce7b11 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2135427 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_CTX_PRIV_H
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#define NVGPU_GR_CTX_PRIV_H
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struct nvgpu_mem;
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struct patch_desc {
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struct nvgpu_mem mem;
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u32 data_count;
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};
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struct zcull_ctx_desc {
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u64 gpu_va;
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u32 ctx_sw_mode;
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};
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struct pm_ctx_desc {
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struct nvgpu_mem mem;
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u64 gpu_va;
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u32 pm_mode;
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};
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struct nvgpu_gr_ctx_desc {
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u32 size[NVGPU_GR_CTX_COUNT];
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#ifdef CONFIG_NVGPU_GRAPHICS
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bool force_preemption_gfxp;
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#endif
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#ifdef CONFIG_NVGPU_CILP
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bool force_preemption_cilp;
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#endif
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bool dump_ctxsw_stats_on_channel_close;
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};
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struct nvgpu_gr_ctx {
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u32 ctx_id;
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bool ctx_id_valid;
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struct nvgpu_mem mem;
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#ifdef CONFIG_NVGPU_GRAPHICS
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struct nvgpu_mem preempt_ctxsw_buffer;
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struct nvgpu_mem spill_ctxsw_buffer;
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struct nvgpu_mem betacb_ctxsw_buffer;
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struct nvgpu_mem pagepool_ctxsw_buffer;
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struct nvgpu_mem gfxp_rtvcb_ctxsw_buffer;
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#endif
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struct patch_desc patch_ctx;
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struct zcull_ctx_desc zcull_ctx;
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struct pm_ctx_desc pm_ctx;
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u32 graphics_preempt_mode;
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u32 compute_preempt_mode;
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bool golden_img_loaded;
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#ifdef CONFIG_NVGPU_CILP
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bool cilp_preempt_pending;
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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bool boosted_ctx;
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#endif
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#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
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u64 virt_ctx;
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#endif
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u64 global_ctx_buffer_va[NVGPU_GR_CTX_VA_COUNT];
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u32 global_ctx_buffer_index[NVGPU_GR_CTX_VA_COUNT];
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bool global_ctx_buffer_mapped;
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u32 tsgid;
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};
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#endif /* NVGPU_GR_CTX_PRIV_H */
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