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20fcf813dd
Some functions are not accessing hardware directly but are being called using HAL ops: For example .init = gv100_bios_init, .preos_wait_for_halt = gv100_bios_preos_wait_for_halt, .preos_reload_check = gv100_bios_preos_reload_check, .devinit = gp106_bios_devinit, .preos = gp106_bios_preos, .verify_devinit = NULL, This was being called as: g->ops.bios.init(g) g->ops.bios.preos_wait_for_halt(g) g->ops.bios.preos_reload_check(g) g->ops.bios.preos(g) g->ops.bios.devinit(g) g->ops.bios.verify_devinit(g) Change the function access by using sw ops, like: Create new function: nvgpu_bios_sw_init() and based on hardware chip call the chip specific bios sw init function: nvgpu_gv100_bios_sw_init() and nvgpu_tu104_bios_sw_init()to assign the sw ops JIRA NVGPU-2071 Change-Id: Ibfcd9b225a7bc184737abdd94c2e54190fcd90a0 Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2108526 GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
106 lines
3.4 KiB
C
106 lines
3.4 KiB
C
/*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvlink_bios.h>
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#include <nvgpu/string.h>
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#include <nvgpu/bios.h>
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int nvgpu_bios_get_nvlink_config_data(struct gk20a *g)
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{
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int ret = 0;
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struct nvlink_config_data_hdr_v1 config;
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if (g->bios->nvlink_config_data_offset == 0U) {
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return -EINVAL;
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}
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nvgpu_memcpy((u8 *)&config,
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&g->bios->data[g->bios->nvlink_config_data_offset],
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sizeof(config));
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if (config.version != NVLINK_CONFIG_DATA_HDR_VER_10) {
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nvgpu_err(g, "unsupported nvlink bios version: 0x%x",
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config.version);
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return -EINVAL;
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}
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switch (config.hdr_size) {
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case NVLINK_CONFIG_DATA_HDR_12_SIZE:
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g->nvlink.ac_coupling_mask = config.ac_coupling_mask;
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g->nvlink.train_at_boot = config.train_at_boot;
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g->nvlink.link_disable_mask = config.link_disable_mask;
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g->nvlink.link_mode_mask = config.link_mode_mask;
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g->nvlink.link_refclk_mask = config.link_refclk_mask;
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break;
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case NVLINK_CONFIG_DATA_HDR_11_SIZE:
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g->nvlink.train_at_boot = config.train_at_boot;
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g->nvlink.link_disable_mask = config.link_disable_mask;
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g->nvlink.link_mode_mask = config.link_mode_mask;
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g->nvlink.link_refclk_mask = config.link_refclk_mask;
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break;
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case NVLINK_CONFIG_DATA_HDR_10_SIZE:
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g->nvlink.link_disable_mask = config.link_disable_mask;
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g->nvlink.link_mode_mask = config.link_mode_mask;
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g->nvlink.link_refclk_mask = config.link_refclk_mask;
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break;
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default:
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nvgpu_err(g, "invalid nvlink bios config size");
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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int nvgpu_bios_get_lpwr_nvlink_table_hdr(struct gk20a *g)
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{
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struct lpwr_nvlink_table_hdr_v1 hdr;
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u8 *lpwr_nvlink_tbl_hdr_ptr = NULL;
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lpwr_nvlink_tbl_hdr_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
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nvgpu_bios_get_bit_token(g,
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NVGPU_BIOS_PERF_TOKEN),
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LPWR_NVLINK_TABLE);
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if (lpwr_nvlink_tbl_hdr_ptr == NULL) {
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nvgpu_err(g, "Invalid pointer to LPWR_NVLINK_TABLE\n");
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return -EINVAL;
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}
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nvgpu_memcpy((u8 *)&hdr, lpwr_nvlink_tbl_hdr_ptr,
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LPWR_NVLINK_TABLE_10_HDR_SIZE_06);
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if (hdr.version != LWPR_NVLINK_TABLE_10_HDR_VER_10) {
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nvgpu_err(g, "Unsupported LPWR_NVLINK_TABLE version: 0x%x",
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hdr.version);
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return -EINVAL;
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}
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g->nvlink.initpll_ordinal =
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BIOS_GET_FIELD(u8, hdr.line_rate_initpll_ordinal,
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VBIOS_LPWR_NVLINK_TABLE_HDR_INITPLL_ORDINAL);
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nvgpu_log(g, gpu_dbg_nvlink, " Nvlink initpll_ordinal: 0x%x",
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g->nvlink.initpll_ordinal);
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return 0;
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}
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