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7cae3709e0
Moved gv11b_fb_intr_inject_hubmmu_ecc_error from fb_intr_ecc_gv11b.c to fusa version and deleted that file. Moved debugger related functions from fb_gm20b.c to fusa version. Updated arch yaml to reflect the fusa and non-fusa fb units. JIRA NVGPU-3690 Change-Id: I929169e9aac62e8377e4ea7e8353caa970999299 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2156879 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
94 lines
2.7 KiB
C
94 lines
2.7 KiB
C
/*
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* GM20B GPC MMU
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifdef CONFIG_NVGPU_TRACE
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#include <trace/events/gk20a.h>
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#endif
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#include <nvgpu/sizes.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/ltc.h>
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#include "fb_gm20b.h"
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#include <nvgpu/io.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/hw/gm20b/hw_fb_gm20b.h>
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#define VPR_INFO_FETCH_WAIT (5)
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#define WPR_INFO_ADDR_ALIGNMENT 0x0000000c
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void fb_gm20b_init_fs_state(struct gk20a *g)
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{
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nvgpu_log_info(g, "initialize gm20b fb");
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gk20a_writel(g, fb_fbhub_num_active_ltcs_r(),
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nvgpu_ltc_get_ltc_count(g));
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if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
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/* Bypass MMU check for non-secure boot. For
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* secure-boot,this register write has no-effect */
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gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffffU);
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}
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}
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void gm20b_fb_set_mmu_page_size(struct gk20a *g)
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{
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/* set large page size in fb */
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u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r());
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fb_mmu_ctrl |= fb_mmu_ctrl_use_pdb_big_page_size_true_f();
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gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
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}
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#ifdef CONFIG_NVGPU_COMPRESSION
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bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g)
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{
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/* set large page size in fb */
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u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r());
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fb_mmu_ctrl |= fb_mmu_ctrl_use_full_comp_tag_line_true_f();
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gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl);
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return true;
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}
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u64 gm20b_fb_compression_page_size(struct gk20a *g)
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{
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return SZ_128K;
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}
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unsigned int gm20b_fb_compressible_page_size(struct gk20a *g)
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{
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return (unsigned int)SZ_64K;
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}
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u64 gm20b_fb_compression_align_mask(struct gk20a *g)
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{
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return SZ_64K - 1UL;
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}
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#endif
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