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7885500a42
Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I1474065f4b552112786974a16cdf076c5179540e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1565880 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
81 lines
2.9 KiB
C
81 lines
2.9 KiB
C
/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _CLK_ARB_H_
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#define _CLK_ARB_H_
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struct gk20a;
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struct nvgpu_clk_session;
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int nvgpu_clk_arb_init_arbiter(struct gk20a *g);
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int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
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u16 *min_mhz, u16 *max_mhz);
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int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
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u32 api_domain, u16 *actual_mhz);
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int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
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u32 api_domain, u16 *effective_mhz);
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int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
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u32 api_domain, u32 *max_points, u16 *fpoints);
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u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g);
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bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain);
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void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g);
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int nvgpu_clk_arb_install_session_fd(struct gk20a *g,
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struct nvgpu_clk_session *session);
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int nvgpu_clk_arb_init_session(struct gk20a *g,
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struct nvgpu_clk_session **_session);
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void nvgpu_clk_arb_release_session(struct gk20a *g,
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struct nvgpu_clk_session *session);
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int nvgpu_clk_arb_commit_request_fd(struct gk20a *g,
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struct nvgpu_clk_session *session, int request_fd);
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int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
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int fd, u32 api_domain, u16 target_mhz);
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int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
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u32 api_domain, u16 *target_mhz);
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int nvgpu_clk_arb_install_event_fd(struct gk20a *g,
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struct nvgpu_clk_session *session, int *event_fd, u32 alarm_mask);
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int nvgpu_clk_arb_install_request_fd(struct gk20a *g,
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struct nvgpu_clk_session *session, int *event_fd);
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void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g);
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int nvgpu_clk_arb_get_current_pstate(struct gk20a *g);
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void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
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void nvgpu_clk_arb_schedule_alarm(struct gk20a *g, u32 alarm);
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#endif /* _CLK_ARB_H_ */
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