Alex Frid 14f47ad1f0 gpu: nvgpu: Update GM20b GPCPLL initial configuration ...

- Set initial output rate to 1/3 of VCO minimum.
- Cleared global BYPASSCTRL to get ready for enabling PLL (this
  won't bring PLL out of bypass, since SEL_VCO register is cleared).
- Added debugfs nodes for BYPASSCTRL and SEL_VCO state.

Bug 1450787

Change-Id: I10b068b006b7e9fbdf7854eff0cfd5cfdc1dd546
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/447750
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

2015-03-18 12:10:37 -07:00

..

nvgpu

gpu: nvgpu: Update GM20b GPCPLL initial configuration

2015-03-18 12:10:37 -07:00