mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 09:57:08 +03:00
d71d38087d
Code touching timer registers was combined with bus code. They're two logically separate register spaces, so separate the code accordingly. JIRA NVGPU-588 Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730893 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
66 lines
2.3 KiB
C
66 lines
2.3 KiB
C
/*
|
|
* GM20B MMU
|
|
*
|
|
* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <nvgpu/timers.h>
|
|
#include <nvgpu/mm.h>
|
|
#include <nvgpu/enabled.h>
|
|
|
|
#include "gk20a/gk20a.h"
|
|
#include "bus_gm20b.h"
|
|
|
|
#include <nvgpu/hw/gm20b/hw_bus_gm20b.h>
|
|
|
|
int gm20b_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
|
|
{
|
|
struct nvgpu_timeout timeout;
|
|
int err = 0;
|
|
u64 iova = nvgpu_inst_block_addr(g, bar1_inst);
|
|
u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v());
|
|
|
|
nvgpu_log_info(g, "bar1 inst block ptr: 0x%08x", ptr_v);
|
|
|
|
gk20a_writel(g, bus_bar1_block_r(),
|
|
nvgpu_aperture_mask(g, bar1_inst,
|
|
bus_bar1_block_target_sys_mem_ncoh_f(),
|
|
bus_bar1_block_target_sys_mem_coh_f(),
|
|
bus_bar1_block_target_vid_mem_f()) |
|
|
bus_bar1_block_mode_virtual_f() |
|
|
bus_bar1_block_ptr_f(ptr_v));
|
|
nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
|
|
do {
|
|
u32 val = gk20a_readl(g, bus_bind_status_r());
|
|
u32 pending = bus_bind_status_bar1_pending_v(val);
|
|
u32 outstanding = bus_bind_status_bar1_outstanding_v(val);
|
|
if (!pending && !outstanding)
|
|
break;
|
|
|
|
nvgpu_udelay(5);
|
|
} while (!nvgpu_timeout_expired(&timeout));
|
|
|
|
if (nvgpu_timeout_peek_expired(&timeout))
|
|
err = -EINVAL;
|
|
|
|
return err;
|
|
}
|