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90b0bf98ac
Add NVGPU_DBG_GPU_IOCTL_CYCLE_STATS to debugger node, to install/uninstall a buffer for cycle stats. Add NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT to debugger node, to attach/flush/detach a buffer for Mode-E streamout. Those ioctls will apply to the first channel in the debug session. Bug 200464613 Jira NVGPU-1442 Change-Id: I0b96d9a07c016690140292fa5886fda545697ee6 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2002060 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
58 lines
2.0 KiB
C
58 lines
2.0 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __NVGPU_IOCTL_CHANNEL_H__
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#define __NVGPU_IOCTL_CHANNEL_H__
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#include <linux/fs.h>
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#include <nvgpu/cyclestats_snapshot.h>
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struct inode;
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struct file;
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struct gk20a;
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struct nvgpu_channel_open_args;
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struct gk20a_cs_snapshot_client_linux {
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struct gk20a_cs_snapshot_client cs_client;
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u32 dmabuf_fd;
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struct dma_buf *dma_handler;
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};
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int gk20a_channel_open(struct inode *inode, struct file *filp);
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int gk20a_channel_release(struct inode *inode, struct file *filp);
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long gk20a_channel_ioctl(struct file *filp,
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unsigned int cmd, unsigned long arg);
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int gk20a_channel_open_ioctl(struct gk20a *g,
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struct nvgpu_channel_open_args *args);
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int gk20a_channel_cycle_stats(struct channel_gk20a *ch, int dmabuf_fd);
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void gk20a_channel_free_cycle_stats_buffer(struct channel_gk20a *ch);
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int gk20a_attach_cycle_stats_snapshot(struct channel_gk20a *ch,
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u32 dmabuf_fd,
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u32 perfmon_id_count,
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u32 *perfmon_id_start);
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int gk20a_flush_cycle_stats_snapshot(struct channel_gk20a *ch);
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int gk20a_channel_free_cycle_stats_snapshot(struct channel_gk20a *ch);
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extern const struct file_operations gk20a_channel_ops;
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u32 nvgpu_get_common_runlist_level(u32 level);
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u32 nvgpu_get_ioctl_graphics_preempt_mode_flags(u32 graphics_preempt_mode_flags);
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u32 nvgpu_get_ioctl_compute_preempt_mode_flags(u32 compute_preempt_mode_flags);
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u32 nvgpu_get_ioctl_graphics_preempt_mode(u32 graphics_preempt_mode);
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u32 nvgpu_get_ioctl_compute_preempt_mode(u32 compute_preempt_mode);
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#endif
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