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linux-nvgpu/drivers/gpu/nvgpu/hal/gr/init
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Vinod G cf45e7914f gpu: nvgpu: gr/init MISRA fixes for Rule 10.x 
Fix MISRA violations for Rule 10.6 and 10.8 in gr.init unit
Assigning composite expression of width 32 to a target of width 64.
Cast from 32 bit width to a wider 64 bit type.

Jira NVGPU-3390
Jira NVGPU-3391

Change-Id: Id06fa9c90ae6cea1a7251b7834aca3f2c2f76e53
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116154
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 08:49:43 -07:00
..
gr_init_gm20b.c
gpu: nvgpu: gr/init MISRA fixes for Rule 10.x
2019-05-10 08:49:43 -07:00
gr_init_gm20b.h
gpu: nvgpu: Fix MISRA Rule 10.3 errors in gr.init
2019-05-09 21:15:24 -07:00
gr_init_gp10b.c
gpu: nvgpu: gr/init MISRA fixes for Rule 10.x
2019-05-10 08:49:43 -07:00
gr_init_gp10b.h
gpu: nvgpu: Fix MISRA Rule 10.3 errors in gr.init
2019-05-09 21:15:24 -07:00
gr_init_gv11b.c
gpu: nvgpu: gr/init MISRA fixes for Rule 10.x
2019-05-10 08:49:43 -07:00
gr_init_gv11b.h
gpu: nvgpu: fix MISRA 17.7 violation in gr.fs_state unit
2019-05-08 15:26:03 -07:00
gr_init_gv100.c
gpu: nvgpu: add hal.gr.init hals to get preemption buffer sizes
2019-03-30 00:34:07 -07:00
gr_init_gv100.h
gpu: nvgpu: add hal.gr.init hals to get preemption buffer sizes
2019-03-30 00:34:07 -07:00
gr_init_tu104.c
gpu: nvgpu: Fix MISRA Rule 10.3 errors in gr.init
2019-05-09 21:15:24 -07:00
gr_init_tu104.h
gpu: nvgpu: add hal.gr.init hals to get preemption buffer sizes
2019-03-30 00:34:07 -07:00