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git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
b82f2075ae
Created gr falcon hal unit with moving following hal functions from gr to gr falcon: u32 (*fecs_base_addr)(void); u32 (*gpccs_base_addr)(void); void (*dump_stats)(struct gk20a *g); u32 (*fecs_ctxsw_mailbox_size)(void); u32 (*get_fecs_ctx_state_store_major_rev_id)(struct gk20a *g); Modified chip hals to populate these new functions and related code now refers to gr falcon hals. Modified kernel headers to have following defs for fecs/gpccs base address in gm20b/gp10b/gv11b/tu104: static inline u32 gr_fecs_irqsset_r(void); static inline u32 gr_gpcs_gpccs_irqsset_r(void); Created base gm20b hals for fecs/gpccs_base_addr and removed redundant gp106 related hals. JIRA NVGPU-1881 Change-Id: I16e820cc1c89223f57988f1e5723fd8fdcbfe89d Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2081245 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
80 lines
2.5 KiB
C
80 lines
2.5 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/falcon.h>
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#include "falcon_sw_gk20a.h"
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void gk20a_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
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{
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struct gk20a *g = flcn->g;
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struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
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&flcn->flcn_engine_dep_ops;
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switch (flcn->flcn_id) {
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case FALCON_ID_PMU:
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flcn_eng_dep_ops->reset_eng = g->ops.pmu.pmu_reset;
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break;
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default:
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/* NULL assignment make sure
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* CPU hard reset in gk20a_falcon_reset() gets execute
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* if falcon doesn't need specific reset implementation
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*/
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flcn_eng_dep_ops->reset_eng = NULL;
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break;
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}
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}
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void gk20a_falcon_sw_init(struct nvgpu_falcon *flcn)
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{
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struct gk20a *g = flcn->g;
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switch (flcn->flcn_id) {
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case FALCON_ID_PMU:
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flcn->flcn_base = g->ops.pmu.falcon_base_addr();
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = true;
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break;
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case FALCON_ID_FECS:
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flcn->flcn_base = g->ops.gr.falcon.fecs_base_addr();
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = false;
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break;
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case FALCON_ID_GPCCS:
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flcn->flcn_base = g->ops.gr.falcon.gpccs_base_addr();
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = false;
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break;
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default:
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flcn->is_falcon_supported = false;
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break;
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}
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if (flcn->is_falcon_supported) {
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gk20a_falcon_engine_dependency_ops(flcn);
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} else {
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nvgpu_log_info(g, "falcon 0x%x not supported on %s",
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flcn->flcn_id, g->name);
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}
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}
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