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17486ec1f6
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct channel_gk20a to struct nvgpu_channel Jira NVGPU-3248 Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2112424 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
90 lines
3.1 KiB
C
90 lines
3.1 KiB
C
/*
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* GK20A USERD
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*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bug.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/nvgpu_mem.h>
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#include "userd_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
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void gk20a_userd_init_mem(struct gk20a *g, struct nvgpu_channel *c)
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{
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struct nvgpu_mem *mem = c->userd_mem;
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u32 offset = c->userd_offset / U32(sizeof(u32));
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nvgpu_log_fn(g, " ");
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nvgpu_mem_wr32(g, mem, offset + ram_userd_put_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_get_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_ref_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_put_hi_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_top_level_get_hi_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_get_hi_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_get_w(), 0);
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nvgpu_mem_wr32(g, mem, offset + ram_userd_gp_put_w(), 0);
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}
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u32 gk20a_userd_gp_get(struct gk20a *g, struct nvgpu_channel *c)
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{
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u64 userd_gpu_va = gk20a_channel_userd_gpu_va(c);
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u64 addr = userd_gpu_va + sizeof(u32) * ram_userd_gp_get_w();
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BUG_ON(u64_hi32(addr) != 0U);
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return nvgpu_bar1_readl(g, (u32)addr);
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}
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u64 gk20a_userd_pb_get(struct gk20a *g, struct nvgpu_channel *c)
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{
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u64 userd_gpu_va = gk20a_channel_userd_gpu_va(c);
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u64 lo_addr = userd_gpu_va + sizeof(u32) * ram_userd_get_w();
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u64 hi_addr = userd_gpu_va + sizeof(u32) * ram_userd_get_hi_w();
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u32 lo, hi;
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BUG_ON((u64_hi32(lo_addr) != 0U) || (u64_hi32(hi_addr) != 0U));
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lo = nvgpu_bar1_readl(g, (u32)lo_addr);
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hi = nvgpu_bar1_readl(g, (u32)hi_addr);
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return ((u64)hi << 32) | lo;
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}
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void gk20a_userd_gp_put(struct gk20a *g, struct nvgpu_channel *c)
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{
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u64 userd_gpu_va = gk20a_channel_userd_gpu_va(c);
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u64 addr = userd_gpu_va + sizeof(u32) * ram_userd_gp_put_w();
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BUG_ON(u64_hi32(addr) != 0U);
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nvgpu_bar1_writel(g, (u32)addr, c->gpfifo.put);
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}
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u32 gk20a_userd_entry_size(struct gk20a *g)
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{
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return BIT32(ram_userd_base_shift_v());
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}
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