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17bc6e6457
Fix below sparse warning by declaring gp10b_write_dmatrfbase() as static kernel-t18x/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c:227:6: warning: symbol 'gp10b_write_dmatrfbase' was not declared. Should it be static? Bug 200088648 Change-Id: I3bd2eeaeb7234ab54d7e9342a7512ec28388f751 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/801213 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
253 lines
7.1 KiB
C
253 lines
7.1 KiB
C
/*
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* GP10B PMU
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*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/delay.h> /* for udelay */
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#include "gk20a/gk20a.h"
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#include "gk20a/pmu_gk20a.h"
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#include "gm20b/acr_gm20b.h"
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#include "gm20b/pmu_gm20b.h"
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#include "pmu_gp10b.h"
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#include "hw_pwr_gp10b.h"
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#define gp10b_dbg_pmu(fmt, arg...) \
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gk20a_dbg(gpu_dbg_pmu, fmt, ##arg)
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/*!
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* Structure/object which single register write need to be done during PG init
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* sequence to set PROD values.
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*/
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struct pg_init_sequence_list {
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u32 regaddr;
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u32 writeval;
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};
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/* PROD settings for ELPG sequencing registers*/
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static struct pg_init_sequence_list _pginitseq_gp10b[] = {
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{0x0010ab10, 0x0000868B} ,
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{0x0010e118, 0x8590848F} ,
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{0x0010e000, 0} ,
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{0x0010e06c, 0x000000A3} ,
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{0x0010e06c, 0x000000A0} ,
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{0x0010e06c, 0x00000095} ,
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{0x0010e06c, 0x000000A6} ,
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{0x0010e06c, 0x0000008C} ,
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{0x0010e06c, 0x00000080} ,
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{0x0010e06c, 0x00000081} ,
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{0x0010e06c, 0x00000087} ,
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{0x0010e06c, 0x00000088} ,
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{0x0010e06c, 0x0000008D} ,
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{0x0010e06c, 0x000000A00} ,
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{0x0010e06c, 0x000000A01} ,
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{0x0010e06c, 0x000000A02} ,
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{0x0010e06c, 0x000000A03} ,
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{0x0010e06c, 0x000000A04} ,
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{0x0010e06c, 0x000000A05} ,
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{0x0010e06c, 0x000000A06} ,
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{0x0010e06c, 0x000000A07} ,
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{0x0010e06c, 0x000000A08} ,
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{0x0010e06c, 0x000000A09} ,
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{0x0010e06c, 0x000000950} ,
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{0x0010e06c, 0x000000951} ,
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{0x0010e06c, 0x000000952} ,
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{0x0010e06c, 0x000000953} ,
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{0x0010e06c, 0x000000954} ,
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{0x0010e06c, 0x000000955} ,
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{0x0010e06c, 0x000000956} ,
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{0x0010e06c, 0x000000957} ,
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{0x0010ab14, 0x00000000} ,
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{0x0010e024, 0x00000000} ,
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{0x0010e028, 0x00000000} ,
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{0x0010e11c, 0x00000000} ,
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{0x0010ab1c, 0x140B0B55} ,
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{0x0010e020, 0x0E262655} ,
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{0x0010e124, 0x25101055} ,
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{0x0010ab20, 0x89abcdef} ,
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{0x0010ab24, 0x00000000} ,
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{0x0010e02c, 0x89abcdef} ,
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{0x0010e030, 0x00000000} ,
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{0x0010e128, 0x89abcdef} ,
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{0x0010e12c, 0x00000000} ,
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{0x0010ab28, 0x75555555} ,
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{0x0010ab2c, 0x70000000} ,
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{0x0010e034, 0x75555555} ,
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{0x0010e038, 0x70000000} ,
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{0x0010e130, 0x75555555} ,
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{0x0010e134, 0x70000000} ,
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{0x0010ab30, 0x00000000} ,
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{0x0010ab34, 0x00000001} ,
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{0x00020004, 0x00000000} ,
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{0x0010e138, 0x00000000} ,
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{0x0010e040, 0x00000000} ,
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{0x0010e168, 0x00000000} ,
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{0x0010e114, 0x0000A5A4} ,
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{0x0010e110, 0x00000000} ,
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{0x0010e10c, 0x8590848F} ,
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{0x0010e05c, 0x00000000} ,
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{0x0010e044, 0x00000000} ,
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{0x0010a644, 0x0000868B} ,
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{0x0010a648, 0x00000000 } ,
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{0x0010a64c, 0x00829493 } ,
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{0x0010a650, 0x00000000} ,
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{0x0010e000, 0} ,
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{0x0010e068, 0x000000A3} ,
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{0x0010e068, 0x000000A0} ,
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{0x0010e068, 0x00000095} ,
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{0x0010e068, 0x000000A6} ,
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{0x0010e068, 0x0000008C} ,
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{0x0010e068, 0x00000080} ,
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{0x0010e068, 0x00000081} ,
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{0x0010e068, 0x00000087} ,
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{0x0010e068, 0x00000088} ,
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{0x0010e068, 0x0000008D} ,
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{0x0010e068, 0x000000A00} ,
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{0x0010e068, 0x000000A01} ,
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{0x0010e068, 0x000000A02} ,
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{0x0010e068, 0x000000A03} ,
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{0x0010e068, 0x000000A04} ,
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{0x0010e068, 0x000000A05} ,
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{0x0010e068, 0x000000A06} ,
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{0x0010e068, 0x000000A07} ,
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{0x0010e068, 0x000000A08} ,
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{0x0010e068, 0x000000A09} ,
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{0x0010e068, 0x000000950} ,
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{0x0010e068, 0x000000951} ,
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{0x0010e068, 0x000000952} ,
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{0x0010e068, 0x000000953} ,
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{0x0010e068, 0x000000954} ,
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{0x0010e068, 0x000000955} ,
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{0x0010e068, 0x000000956} ,
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{0x0010e068, 0x000000957} ,
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{0x0010e000, 0} ,
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{0x0010e004, 0x0000008E},
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};
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static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
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u32 flags)
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{
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struct pmu_gk20a *pmu = &g->pmu;
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struct pmu_cmd cmd;
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u32 seq;
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gk20a_dbg_fn("");
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gp10b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone);
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if (g->ops.pmu.lspmuwprinitdone) {
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/* send message to load FECS falcon */
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memset(&cmd, 0, sizeof(struct pmu_cmd));
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cmd.hdr.unit_id = PMU_UNIT_ACR;
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cmd.hdr.size = PMU_CMD_HDR_SIZE +
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sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons);
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cmd.cmd.acr.boot_falcons.cmd_type =
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PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS;
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cmd.cmd.acr.boot_falcons.flags = flags;
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cmd.cmd.acr.boot_falcons.falconidmask =
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falconidmask;
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cmd.cmd.acr.boot_falcons.usevamask = 0;
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cmd.cmd.acr.boot_falcons.wprvirtualbase.lo =
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u64_lo32(g->pmu.wpr_buf.gpu_va);
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cmd.cmd.acr.boot_falcons.wprvirtualbase.hi =
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u64_hi32(g->pmu.wpr_buf.gpu_va);
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gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n",
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falconidmask);
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gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
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pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
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}
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gk20a_dbg_fn("done");
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return;
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}
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static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
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{
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u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
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/* GM20B PMU supports loading FECS and GPCCS only */
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if (falconidmask == 0)
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return -EINVAL;
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if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) |
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(1 << LSF_FALCON_ID_GPCCS)))
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return -EINVAL;
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g->ops.pmu.lsfloadedfalconid = 0;
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/* check whether pmu is ready to bootstrap lsf if not wait for it */
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if (!g->ops.pmu.lspmuwprinitdone) {
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pmu_wait_message_cond(&g->pmu,
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gk20a_get_gr_idle_timeout(g),
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&g->ops.pmu.lspmuwprinitdone, 1);
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/* check again if it still not ready indicate an error */
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if (!g->ops.pmu.lspmuwprinitdone) {
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gk20a_err(dev_from_gk20a(g),
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"PMU not ready to load LSF");
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return -ETIMEDOUT;
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}
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}
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/* load falcon(s) */
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gp10b_pmu_load_multiple_falcons(g, falconidmask, flags);
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pmu_wait_message_cond(&g->pmu,
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gk20a_get_gr_idle_timeout(g),
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&g->ops.pmu.lsfloadedfalconid, falconidmask);
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if (g->ops.pmu.lsfloadedfalconid != falconidmask)
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return -ETIMEDOUT;
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return 0;
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}
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static int gp10b_pmu_setup_elpg(struct gk20a *g)
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{
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int ret = 0;
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u32 reg_writes;
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u32 index;
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gk20a_dbg_fn("");
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if (g->elpg_enabled) {
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reg_writes = ((sizeof(_pginitseq_gp10b) /
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sizeof((_pginitseq_gp10b)[0])));
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/* Initialize registers with production values*/
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for (index = 0; index < reg_writes; index++) {
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gk20a_writel(g, _pginitseq_gp10b[index].regaddr,
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_pginitseq_gp10b[index].writeval);
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}
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}
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gk20a_dbg_fn("done");
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return ret;
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}
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static void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
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{
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gk20a_writel(g, pwr_falcon_dmatrfbase_r(),
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addr);
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gk20a_writel(g, pwr_falcon_dmatrfbase1_r(),
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0x0);
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}
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void gp10b_init_pmu_ops(struct gpu_ops *gops)
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{
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if (gops->privsecurity) {
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gm20b_init_secure_pmu(gops);
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gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
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gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
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} else {
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gk20a_init_pmu_ops(gops);
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gops->pmu.pmu_setup_hw_and_bootstrap =
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gm20b_init_nspmu_setup_hw1;
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gops->pmu.load_lsfalcon_ucode = NULL;
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gops->pmu.init_wpr_region = NULL;
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}
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gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg;
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gops->pmu.lspmuwprinitdone = false;
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gops->pmu.fecsbootstrapdone = false;
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gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase;
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}
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