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Name the Make and C flag variables consistently wih syntax: CONFIG_NVGPU_<feature name> s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS s/NVGPU_USERD/CONFIG_NVGPU_USERD s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU s/NVGPU_VPR/CONFIG_NVGPU_VPR s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG JIRA NVGPU-3624 Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2130290 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
126 lines
3.6 KiB
C
126 lines
3.6 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifdef CONFIG_NVGPU_NVLINK
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/bitops.h>
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#include <nvgpu/nvlink.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvlink_bios.h>
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#include <nvgpu/nvlink_minion.h>
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#include "nvlink_gv100.h"
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#include "nvlink_tu104.h"
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#include <nvgpu/hw/tu104/hw_nvl_tu104.h>
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int tu104_nvlink_rxdet(struct gk20a *g, u32 link_id)
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{
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int ret = 0;
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u32 reg;
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struct nvgpu_timeout timeout;
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ret = g->ops.nvlink.minion.send_dlcmd(g, link_id,
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NVGPU_NVLINK_MINION_DLCMD_INITRXTERM, true);
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if (ret != 0) {
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nvgpu_err(g, "Error during INITRXTERM minion DLCMD on link %u",
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link_id);
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return ret;
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}
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ret = g->ops.nvlink.minion.send_dlcmd(g, link_id,
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NVGPU_NVLINK_MINION_DLCMD_TURING_RXDET, true);
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if (ret != 0) {
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nvgpu_err(g, "Error during RXDET minion DLCMD on link %u",
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link_id);
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return ret;
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}
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ret = nvgpu_timeout_init(g, &timeout, NV_NVLINK_REG_POLL_TIMEOUT_MS,
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NVGPU_TIMER_CPU_TIMER);
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if (ret != 0) {
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nvgpu_err(g, "Error during timeout init");
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return ret;
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}
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do {
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reg = DLPL_REG_RD32(g, link_id, nvl_sl0_link_rxdet_status_r());
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if (nvl_sl0_link_rxdet_status_sts_v(reg) ==
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nvl_sl0_link_rxdet_status_sts_found_v()) {
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nvgpu_log(g, gpu_dbg_nvlink,
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"RXDET successful on link %u", link_id);
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return ret;
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}
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if (nvl_sl0_link_rxdet_status_sts_v(reg) ==
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nvl_sl0_link_rxdet_status_sts_timeout_v()) {
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nvgpu_log(g, gpu_dbg_nvlink,
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"RXDET failed on link %u", link_id);
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break;
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}
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nvgpu_udelay(NV_NVLINK_TIMEOUT_DELAY_US);
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} while (nvgpu_timeout_expired_msg(
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&timeout,
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"RXDET status check timed out on link %u",
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link_id) == 0);
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return -ETIMEDOUT;
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}
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void tu104_nvlink_get_connected_link_mask(u32 *link_mask)
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{
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*link_mask = TU104_CONNECTED_LINK_MASK;
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}
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int tu104_nvlink_speed_config(struct gk20a *g)
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{
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int ret = 0;
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ret = nvgpu_bios_get_lpwr_nvlink_table_hdr(g);
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if (ret != 0) {
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nvgpu_err(g, "Failed to read LWPR_NVLINK_TABLE header\n");
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return ret;
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}
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switch (g->nvlink.initpll_ordinal) {
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case INITPLL_1:
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g->nvlink.speed = nvgpu_nvlink_speed_20G;
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g->nvlink.initpll_cmd = NVGPU_NVLINK_MINION_DLCMD_INITPLL_1;
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break;
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case INITPLL_7:
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g->nvlink.speed = nvgpu_nvlink_speed_16G;
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g->nvlink.initpll_cmd = NVGPU_NVLINK_MINION_DLCMD_INITPLL_7;
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break;
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default:
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nvgpu_err(g, "Nvlink initpll %d from VBIOS not supported.",
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g->nvlink.initpll_ordinal);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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#endif /* CONFIG_NVGPU_NVLINK */
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