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e58e00b0fb
Initialize the clock counters for GPCCLK, XBARCLK, SYSCLK. This INIT was done in PMU before, but now disabled from TU10A profile. Hence the initialization is moved into nvgpu. This patch does the following. 1. Move clock files from GV100 to TU104. 2. Add the Counter HW Registers. 3. Initialize the counter registers for gpc, xbar and sysclk. 4. Change the debug fs node from gv100 to tu104. 5. Update in yaml file with new file names. Bug 200536091 Change-Id: I436019a18f5c4c73979977666d0c04ce4c569047 Signed-off-by: Abdul Salam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2155298 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
40 lines
1.7 KiB
C
40 lines
1.7 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef CLK_TU104_H
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#define CLK_TU104_H
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#include <nvgpu/lock.h>
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#include <nvgpu/gk20a.h>
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u32 tu104_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
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int tu104_init_clk_support(struct gk20a *g);
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u32 tu104_crystal_clk_hz(struct gk20a *g);
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unsigned long tu104_clk_measure_freq(struct gk20a *g, u32 api_domain);
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void tu104_suspend_clk_support(struct gk20a *g);
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int tu104_clk_domain_get_f_points(
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struct gk20a *g,
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u32 clkapidomain,
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u32 *pfpointscount,
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u16 *pfreqpointsinmhz);
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unsigned long tu104_clk_maxrate(struct gk20a *g, u32 api_domain);
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#endif /* CLK_TU104_H */
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