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d5d31e5b17
Fix rule 8.6 misra violation in ltc code by enclosing following functions defs under CONFIG_NVGPU_FALCON_NON_FUSA switch. gp10b_ltc_intr_configure gp10b_ltc_intr_isr gm20b_determine_L2_size_bytes gm20b_ltc_set_enabled gm20b_ltc_init_fs_state Added following functions defs under CONFIG_NVGPU_INJECT_HWERR switch. gv11b_ltc_get_err_desc gv11b_ltc_inject_ecc_error Also added hal initializations under relevant switch. JIRA NVGPU-3872 Change-Id: I6800ae4a8fcd91e534df97e8db7770f0e4e9112a Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2174827 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
59 lines
2.2 KiB
C
59 lines
2.2 KiB
C
/*
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* GM20B L2
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_LTC_GM20B
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#define NVGPU_LTC_GM20B
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#include <nvgpu/types.h>
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struct gk20a;
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void gm20b_flush_ltc(struct gk20a *g);
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#ifdef CONFIG_NVGPU_FALCON_NON_FUSA
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u64 gm20b_determine_L2_size_bytes(struct gk20a *g);
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void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled);
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void gm20b_ltc_init_fs_state(struct gk20a *g);
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#endif
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#ifdef CONFIG_NVGPU_GRAPHICS
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void gm20b_ltc_set_zbc_color_entry(struct gk20a *g,
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u32 *color_l2,
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u32 index);
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void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g,
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u32 depth_val,
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u32 index);
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#endif /* CONFIG_NVGPU_GRAPHICS */
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#ifdef CONFIG_NVGPU_DEBUGGER
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bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr);
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bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr);
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bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr);
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void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
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u32 *priv_addr_table,
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u32 *priv_addr_table_index);
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void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
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u32 *priv_addr_table,
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u32 *priv_addr_table_index);
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#endif /* CONFIG_NVGPU_DEBUGGER */
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#endif
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